JAJSOT1J December   2008  – June 2022 LM5088 , LM5088-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings: LM5088
    3. 6.3 ESD Ratings: LM5088-Q1
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High Voltage Low-Dropout Regulator
      2. 7.3.2  Line Undervoltage Detector
      3. 7.3.3  Oscillator and Sync Capability
      4. 7.3.4  Error Amplifier and PWM Comparator
      5. 7.3.5  Ramp Generator
      6. 7.3.6  Dropout Voltage Reduction
      7. 7.3.7  Frequency Dithering (LM5088-1 Only)
      8. 7.3.8  Cycle-by-Cycle Current Limit
      9. 7.3.9  Overload Protection Timer (LM5088-2 Only)
      10. 7.3.10 Soft Start
      11. 7.3.11 HG Output
      12. 7.3.12 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 EN Pin Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Timing Resistor
        2. 8.2.2.2  Output Inductor
        3. 8.2.2.3  Current Sense Resistor
        4. 8.2.2.4  Ramp Capacitor
        5. 8.2.2.5  Output Capacitors
        6. 8.2.2.6  Input Capacitors
        7. 8.2.2.7  VCC Capacitor
        8. 8.2.2.8  Bootstrap Capacitor
        9. 8.2.2.9  Soft-Start Capacitor
        10. 8.2.2.10 Output Voltage Divider
        11. 8.2.2.11 UVLO Divider
        12. 8.2.2.12 Restart Capacitor (LM5008-2 Only)
        13. 8.2.2.13 MOSFET Selection
        14. 8.2.2.14 Diode Selection
        15. 8.2.2.15 Snubber Components Selection
        16. 8.2.2.16 Error Amplifier Compensation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Thermal Considerations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Electrical Characteristics

See (2)(4)
PARAMETER TEST CONDITIONS TJ = –40°C to +125°C TJ = 25°C UNIT
MIN TYP MAX MIN TYP MAX
VIN SUPPLY
IBIAS VIN operating current VFB = 1.3 V 5.5 3.8 mA
ISTANDBY VIN standby current VEN = 1 V 3.6 2.9 mA
ISHUTDOWN VIN shutdown current VEN = 0 V 26 15 µA
VCC REGULATOR
VVCC(Reg) VCC regulation VVCC = open 7.4 8.2 7.8 V
VVCC(Reg) VCC regulation VVIN = 4.5 V, VVCC = open 4.3 4.5 V
VCC sourcing current limit VVCC = 0 30 35 mA
VVCC(UV) VCC undervoltage lockout threshold Positive going VVCC 3.7 4.2 4 V
VCC undervoltage hysteresis 200 mV
ENABLE THRESHOLDS
EN shutdown threshold VEN rising 320 480 400 mV
EN shutdown hysteresis VEN falling 100 mV
EN standby threshold VEN rising 1.1 1.3 1.2 V
EN standby hysteresis VEN falling 120 mV
EN pullup current source VEN = 0 V 5 µA
SOFT START
SS pullup current source VSS = 0 V 8 13 11 µA
FB to SS offset VFB = 1.3 V 150 mV
ERROR AMPLIFIER
VREF FB reference voltage Measured at FB pin
FB = COMP		 1.187 1.223 1.205 V
FB input bias current VFB = 1.2 V 100 18 nA
COMP sink and source current 3 mA
AOL DC gain 60 dB
FBW Unity gain bandwidth 3 MHz
PWM COMPARATORS
tHG(OFF) Forced HG off time 185 365 280 ns
tON(MIN) Minimum HG on time VVIN = 60 V 55 ns
COMP to PWM comparator offset 930 mV
OSCILLATOR (RT PIN)
LM5088-2 (non-dithering)
fnom1 Nominal oscillator frequency RRT = 31.6 kΩ 180 220 200 kHz
fnom2 RRT = 11.3 kΩ 430 565 500 kHz
LM5088-1 (dithering)
fmin Dithering range Minimum dither frequency fnom – 5% kHz
fmax Maximum dither frequency fnom + 5% kHz
SYNC
SYNC positive threshold 2.3 V
SYNC pulse width 15 150 ns
CURRENT LIMIT
VCS(TH) Cycle-by-cycle sense voltage threshold VRAMP = 0 V 112 136 120 mV
Cycle-by-cycle current limit delay VRAMP = 2.5 V 280 ns
Buck switch VDS protection VIN to SW 1.5 V
CURRENT LIMIT RESTART (RES Pin)
Vresup RES threshold upper (rising) VCS = 0.125 1.1 1.3 1.2 V
Vresdown RES threshold lower (falling) 0.1 0.3 0.2 V
Icharge Charge source current VCS ≥ 0.125 40 65 50 µA
Idischarge Discharge sink current VCS < 0.125 20 34 27 µA
Irampdown Discharge sink current (post fault) 0.8 1.6 1.2 µA
RAMP GENERATOR(1)
IRAMP1 RAMP current 1 VVIN = 60 V, VOUT = 10 V 235 345 295 µA
IRAMP2 RAMP current 2 VVIN = 10 V, VOUT = 10 V 18 30 25 µA
VOUT bias current VOUT = 48 V 250 µA
RAMP output low voltage VVIN = 60 V, VOUT = 10 V 200 mV
HIGH SIDE (HG) GATE DRIVER
VOLH HG low-state output voltage IHG = 100 mA 215 115 mV
VOHH HG high-state output voltage IHG = –100 mA,
VOHH = VBOOT – VHG		 240 mV
HG rise time Cload = 1000 pF 12 ns
HG fall time Cload = 1000 pF 6 ns
IOHH Peak HG source current VHG = 0 V 1.5 A
IOLH Peak HG sink current VHG = VVCC 2 A
BOOT UVLO BOOT to SW 3 V
Pre RDS(ON) Pre-charge switch ON resistance IVCC = 1 mA 72 Ω
Pre-charge switch on time 300 ns
THERMAL(3)
TSD Thermal shutdown temperature Junction temperature rising 165 °C
Thermal shutdown hysteresis Junction temperature falling 25 °C
(1) RAMP and COMP are output pins. As such they are not specified to have an external voltage applied.
(2) Typical specifications represent the most likely parametric norm at 25°C operation.
(3) For detailed information on soldering plastic HTSSOP packages, visit www.ti.com/packaging.
(4) Minimum and maximum limits are specified through test, design, or statistical correlation. Typical values represent at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VVIN = 48 V, VVCC = 8 V, VEN = 5 V, RRT = 31.6 kΩ. No load on HG.