JAJSOT1J December   2008  – June 2022 LM5088 , LM5088-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings: LM5088
    3. 6.3 ESD Ratings: LM5088-Q1
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High Voltage Low-Dropout Regulator
      2. 7.3.2  Line Undervoltage Detector
      3. 7.3.3  Oscillator and Sync Capability
      4. 7.3.4  Error Amplifier and PWM Comparator
      5. 7.3.5  Ramp Generator
      6. 7.3.6  Dropout Voltage Reduction
      7. 7.3.7  Frequency Dithering (LM5088-1 Only)
      8. 7.3.8  Cycle-by-Cycle Current Limit
      9. 7.3.9  Overload Protection Timer (LM5088-2 Only)
      10. 7.3.10 Soft Start
      11. 7.3.11 HG Output
      12. 7.3.12 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 EN Pin Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Timing Resistor
        2. 8.2.2.2  Output Inductor
        3. 8.2.2.3  Current Sense Resistor
        4. 8.2.2.4  Ramp Capacitor
        5. 8.2.2.5  Output Capacitors
        6. 8.2.2.6  Input Capacitors
        7. 8.2.2.7  VCC Capacitor
        8. 8.2.2.8  Bootstrap Capacitor
        9. 8.2.2.9  Soft-Start Capacitor
        10. 8.2.2.10 Output Voltage Divider
        11. 8.2.2.11 UVLO Divider
        12. 8.2.2.12 Restart Capacitor (LM5008-2 Only)
        13. 8.2.2.13 MOSFET Selection
        14. 8.2.2.14 Diode Selection
        15. 8.2.2.15 Snubber Components Selection
        16. 8.2.2.16 Error Amplifier Compensation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Thermal Considerations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.2.4 Ramp Capacitor

With the inductor and sense resistor value selected, the value of the ramp capacitor (CRAMP) necessary for the emulation ramp circuit is given by:

Equation 12. GUID-FF91A433-E432-44E5-AD59-AE88DFADF3F0-low.gif

where

  • L is the value of the output inductor.
  • gm is the ramp generator transconductance (5 µA/V).
  • A is the current sense amplifier gain (10 V/V).

For the current design example, the ramp capacitor is calculated as:

Equation 13. GUID-48B48816-47F3-42C3-B4E6-E96D46F538BA-low.gif

The next lowest standard value, 270 pF, was selected for CRAMP. An NPO capacitor with 5% or better tolerance is recommended. Note that selecting a capacitor value lower than the calculated value increases the slope compensation. Furthermore, selecting a ramp capacitor substantially lower or higher than the calculated value also results in incorrect PWM operation.

For VOUT > 5 V, internal slope compensation provided by the LM5088 may not be adequate for certain operating conditions especially at low input voltages. A pullup resistor may be added from the VCC to RAMP pin to increase the slope compensation. Optimal slope compensation current can be calculated from Equation 14.

Equation 14. IOS = VOUT × 5 µA/V

and RRAMP is given by Equation 15.

Equation 15. GUID-FAEABA31-B4DE-4F5A-8A68-EE3E1635EFCB-low.gif
GUID-B8C22559-2A84-47EA-AED8-6A08B876729E-low.gifFigure 8-3 Additional Slope Compensation for VOUT > 5 V