LM73605/LM73606ファミリのデバイスは、使いやすい同期整流降圧型DC/DCコンバータで、3.5V~36Vの範囲の電源電圧から、最大5A (LM73605)または6A (LM73606)の負荷電流を駆動できます。LM73605/LM73606は、非常に小さなサイズのソリューションでありながら、優れた効率と出力精度を実現しています。ピーク電流モード制御が採用されています。可変スイッチング周波数、外部クロックへの同期、FPWMオプション、パワー・グッド・フラグ、高精度のイネーブル、可変ソフトスタート、トラッキングなどの追加機能により、広範なアプリケーションに対して柔軟で使いやすいソリューションを実現できます。軽負荷時の自動周波数フォールドバックと、オプションの外部バイアスにより、負荷範囲の全体にわたって効率が向上します。このファミリは、必要な外付けコンポーネントが少なく、PCBレイアウトが単純になるようピン配置が設計されており、最適なEMIと熱性能を実現しています。保護機能として、サーマル・シャットダウン、入力低電圧誤動作防止、サイクル単位の電流制限、ヒカップ短絡保護機能が搭載されています。LM73605およびLM73606デバイスはピン互換なので、電流を簡単にスケーリングできます。
型番 | パッケージ | 本体サイズ(公称) |
---|---|---|
LM73605 | WQFN (30) ウェッタブル・フランク |
6.00mm×4.00mm |
LM73606 |
日付 | 改訂内容 | 注 |
---|---|---|
2017年9月 | * | 初版 |
PIN | I/O(1) | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1, 2, 3, 4, 5 | SW | P | Switching output of the regulator. Internally connected to source of the HS FET and drain of the LS FET. Connect to power inductor and bootstrap capacitor. |
6 | CBOOT | P | Bootstrap capacitor connection for HS FET driver. Connect a high-quality 470-nF capacitor from this pin to the SW pin. |
7 | VCC | P | Output of internal bias supply. Used as supply to internal control circuits and drivers. Connect a high-quality 2.2-µF capacitor from this pin to GND. TI does not recommend loading this pin by external circuitry. |
8 | BIAS | P | Optional BIAS LDO supply input. TI recommends tying to VOUT when 3.3 V ≤ VOUT ≤ 18 V, or tie to an external 3.3-V or 5-V rail if available, to improve efficiency. BIAS pin voltage must not be greater than VIN. Tie to ground when not in use. |
9 | RT | A | Switching frequency setting pin. Place a resistor from this pin to ground to set the switching frequency. If floating, the default switching frequency is 500 kHz. Do not short to ground. |
10 | SS/TRK | A | Soft-start control pin. Leave this pin floating for a 5-ms internal soft-start ramp. An external capacitor can be connected from this pin to ground to extend the soft start time. A 2-µA current sourced from this pin charges the capacitor to provide the ramp. Connect to external ramp for tracking. Do not short to ground. |
11 | FB | I | Feedback input for output voltage regulation. Connect a resistor divider to set the output voltage. Never short this pin to ground during operation. |
12–15, 27–30 | NC | — | No internal connection. Connect to ground net and copper to improve heat sinking and board-level reliability. |
16 | PGOOD | O | Open drain power-good flag output. Connect to suitable voltage supply through a current limiting resistor. High = VOUT regulation OK, Low = VOUT regulation fault. PGOOD = LOW when EN = low and VIN > 2 V. |
17 | SYNC/MODE | I | Synchronization input and mode setting pin. Do not float. Tie to ground if not used. Tie to ground: auto mode, higher efficiency at light loads; Tie to logic high: forced PWM, constant switching frequency over load; Tie to external clock source: forced PWM, synchronize to the rising edge of the external clock. |
18 | EN | I | Enable input to regulator. Do not float. High = ON, Low = OFF. Can be tied to PVIN. Precision enable input allows adjustable input voltage UVLO using external resistor divider. |
19 | AGND | G | Analog ground. Ground reference for internal circuitry. All electrical parameters are measured with respect to this pin. Connect to system ground on PCB. |
20–22 | PVIN | P | Supply input to internal bias LDO and HS FET. Connect to input supply and input bypass capacitors CIN. CIN must be placed right next to this pin and PGND pins on PCB, and connected with short and wide traces. |
23–26 | PGND | G | Power ground, connected to the source of LS FET internally. Connect to system ground, DAP/EP, AGND, ground side of CIN and COUT on PCB. Path to CIN must be as short as possible |
EP | DAP | G | Low impedance connection to AGND. Connect to system ground on PCB. Major heat dissipation path for the device. Must be used for heat sinking by soldering to ground copper on PCB. Thermal vias are preferred to improve heat dissipation to other layers. |
PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|
Input voltages | PVIN to PGND | –0.3 | 42 | V |
EN to AGND | –0.3 | VIN + 0.3 | ||
FB, RT, SS/TRK to AGND | –0.3 | 5 | ||
PGOOD to AGND | –0.1 | 20 | ||
SYNC to AGND | –0.3 | 5.5 | ||
BIAS to AGND | –0.3 | Lower of (VIN + 0.3) or 20 | ||
AGND to PGND | –0.3 | 0.3 | ||
Output voltages | SW to PGND | –0.3 | VIN + 0.3 | V |
SW to PGND less than 10-ns transients | –3.5 | 42 | ||
CBOOT to SW | –0.3 | 5 | ||
VCC to AGND | –0.3 | 5 | ||
Operating junction temperature, TJ | –40 | 150 | °C | |
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±750 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Input voltages | PVIN to PGND | 3.5 | 36 | V |
EN | 0 | VIN | ||
FB | 0 | 4.5 | ||
PGOOD | 0 | 18 | ||
BIAS input not used | 0 | 0.3 | ||
BIAS input used | 0 | Lower of (VIN + 0.3) or 18 | ||
AGND to PGND | –0.1 | 0.1 | ||
Output voltage | VOUT | 1 | 95% of VIN | V |
Output current | IOUT, LM73605 | 0 | 5 | A |
IOUT, LM73606 | 0 | 6 | A | |
Temperature | Operating junction temperature, TJ | –40 | 125 | °C |
THERMAL METRIC(1) | LM73605/LM73606 | UNIT | |
---|---|---|---|
RNP (WQFN) | |||
30 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 34.3 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 14.6 | °C/W |
RθJB | Junction-to-board thermal resistance | 7.3 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.1 | °C/W |
ψJB | Junction-to-board characterization parameter | 7.1 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 1 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY VOLTAGE (PVIN PINS) | ||||||
VIN | Operating input voltage range | 3.5 | 36 | V | ||
ISD | Shutdown quiescent current; measured at VIN pin(1) | VEN = 0 V TJ = 25℃ |
0.8 | 10 | µA | |
IQ_NONSW | Operating quiescent current from VIN (non-switching) | VEN = 2 V, VFB = 1.5 V, VBIAS = 3.3 V external | 0.6 | 12 | µA | |
ENABLE (EN PIN) | ||||||
VEN_VCC_H | Enable input high level for VCC output | VEN rising | 1.15 | V | ||
VEN_VCC_L | Enable input low level for VCC output | VEN falling | 0.3 | V | ||
VEN_VOUT_H | Enable input high level for VOUT | VEN rising | 1.14 | 1.196 | 1.25 | V |
VEN_VOUT_HYS | Enable input hysteresis for VOUT | VEN falling hysteresis | –100 | mV | ||
ILKG_EN | Enable input leakage current | VEN = 2 V | 1.4 | 200 | nA | |
INTERNAL LDO (VCC PIN, BIAS PIN) | ||||||
VCC | Internal VCC voltage | PWM operation | 3.27 | V | ||
PFM operation | 3.1 | V | ||||
VCC_UVLO | Internal VCC undervoltage lockout | VCC rising | 2.96 | 3.14 | 3.27 | V |
VCC falling hysteresis | –605 | mV | ||||
VBIAS_ON | Input changeover | VBIAS rising | 3.09 | 3.25 | V | |
VBIAS falling hysteresis | –63 | mV | ||||
IBIAS_NONSW | Operating quiescent current from external VBIAS (non-switching) | VEN = 2 V, VFB = 1.5 V, VBIAS = 3.3 V external | 21 | 50 | µA | |
VOLTAGE REFERENCE (FB PIN) | ||||||
VFB | Feedback voltage | PWM mode | 0.987 | 1.006 | 1.017 | V |
ILKG_FB | Input leakage current at FB pin | VFB = 1 V | 0.2 | 60 | nA | |
HIGH SIDE DRIVER (CBOOT PIN) | ||||||
VCBOOT_UVLO | CBOOT - SW undervoltage lockout | 1.6 | 2.2 | 2.7 | V | |
CURRENT LIMITS AND HICCUP | ||||||
IHS_LIMIT | Short-circuit, high-side current limit(2) | LM73605 | 6 | 7.3 | 8.35 | A |
LM73606 | 7.4 | 8.7 | 9.85 | |||
ILS_LIMIT | Low-side current limit(2) | LM73605 | 4.79 | 5.5 | 6.1 | A |
LM73606 | 5.8 | 6.6 | 7.25 | |||
INEG_LIMIT | Negative current limit | LM73605 | –5 | A | ||
LM73606 | –6 | |||||
VHICCUP | Hiccup threshold on FB pin | 0.36 | 0.4 | 0.44 | V | |
IL_ZC | Zero cross-current limit | 0.06 | A | |||
SOFT START (SS/TRK PIN) | ||||||
ISSC | Soft-start charge current | 1.8 | 2 | 2.2 | µA | |
RSSD | Soft-start discharge resistance | UVLO, TSD, OCP, or EN = 0 | 1 | kΩ | ||
POWER GOOD (PGOOD PIN) and OVERVOLTAGE PROTECTION | ||||||
VPGOOD_OV | Power-good overvoltage threshold | % of FB voltage | 106% | 110% | 113% | |
VPGOOD_UV | Power-good undervoltage threshold | % of FB voltage | 86% | 90% | 93% | |
VPGOOD_HYS | Power-good hysteresis | % of FB voltage | 1.2% | |||
VPGOOD_VALID | Minimum input voltage for proper PGOOD function | 50-µA pullup to PGOOD pin, VEN = 0 V, TJ = 25°C | 1.3 | 2 | V | |
RPGOOD | Power-good ON-resistance | VEN = 2.5V | 40 | 100 | Ω | |
VEN = 0 V | 30 | 90 | ||||
MOSFETS | ||||||
RDS_ON_HS (3) | High-side MOSFET ON-resistance | IOUT = 1 A, VBIAS = VOUT = 3.3 V | 53 | 90 | mΩ | |
RDS_ON_LS (3) | Low-side MOSFET ON-resistance | IOUT = 1 A, VBIAS = VOUT = 3.3 V | 31 | 55 | mΩ | |
THERMAL SHUTDOWN | ||||||
TSD (4) | Thermal shutdown threshold | Shutdown threshold | 160 | °C | ||
Recovery threshold | 135 | °C |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
CURRENT LIMITS AND HICCUP | ||||||
NOC (1) | Number of switching cycles before hiccup is tripped | 128 | Cycles | |||
tOC | Overcurrent hiccup retry delay time | 46 | ms | |||
SOFT START (SS/TRK PIN) | ||||||
tSS | Internal soft-start time | CSS = OPEN, from EN rising edge to PGOOD rising edge | 3.5 | 6.3 | ms | |
POWER GOOD (PGOOD PIN) and OVERVOLTAGE PROTECTION | ||||||
tPGOOD_RISE | PGOOD rising edge deglitch delay | 80 | 140 | 200 | µs | |
tPGOOD_FALL | PGOOD falling edge deglitch delay | 80 | 140 | 200 | µs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
PWM LIMITS (SW PINS) | ||||||
tON-MIN | Minimum switch on-time | 60 | 82 | ns | ||
tOFF-MIN | Minimum switch off-time | 70 | 120 | ns | ||
tON-MAX | Maximum switch on-time | HS timeout in dropout | 3 | 6 | 9 | µs |
OSCILLATOR (RT and SYNC PINS) | ||||||
fOSC | Internal oscillator frequency | RT = Open | 440 | 500 | 560 | kHz |
fADJ | Minimum adjustable frequency by RT or SYNC | RT =115 kΩ, 0.1% | 315 | 350 | 385 | kHz |
Maximum adjustable frequency by RT or SYNC | RT = 17.4 kΩ, 0.1% | 1980 | 2200 | 2420 | kHz | |
VSYNC_HIGH | Sync input high level threshold | 2 | V | |||
VSYNC_LOW | Sync input low level threshold | 0.4 | V | |||
VMODE_HIGH | Mode input high level threshold for FPWM | 0.42 | V | |||
VMODE_LOW | Mode input low level threshold for AUTO mode | 0.4 | V | |||
tSYNC_MIN | Sync input minimum ON and OFF-time | 80 | ns |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VFB_PFM | Output voltage offset at no load in auto mode | VIN = 3.8 V to 36 V, VSYNC = 0 V, auto mode IOUT = 0 A | 2% | |||
VDROP | Minimum input to output voltage differential to maintain specified accuracy | VOUT = 5 V, IOUT = 3 A, fSW = 2.2 MHz | 0.4 | V | ||
IQ_SW | Operating quiescent current (switching) | VEN = 3.3 V, IOUT = 0 A, RT = open, VBIAS = VOUT = 3.3 V , RFBT = 1 Meg | 15 | µA | ||
IPEAK_MIN | Minimum inductor peak current | LM73605 : VSYNC = 0, IOUT = 10 mA |
1 | A | ||
LM73606 : VSYNC = 0 V, IOUT = 10 mA |
1.3 | |||||
IBIAS_SW | Operating quiescent current from external VBIAS (switching) | fSW = 500 kHz, IOUT = 1 A | 7 | mA | ||
fSW = 2.2 MHz, IOUT = 1 A | 25 | |||||
DMAX | Maximum switch duty cycle | While in frequency foldback | 97.5% | |||
tDEAD | Dead time between high-side and low-side MOSFETs | 4 | ns |