LM73605/LM73606ファミリのデバイスは、使いやすい同期整流降圧型DC/DCコンバータで、3.5V~36Vの範囲の電源電圧から、最大5A (LM73605)または6A (LM73606)の負荷電流を駆動できます。LM73605/LM73606は、非常に小さなサイズのソリューションでありながら、優れた効率と出力精度を実現しています。ピーク電流モード制御が採用されています。可変スイッチング周波数、外部クロックへの同期、FPWMオプション、パワー・グッド・フラグ、高精度のイネーブル、可変ソフトスタート、トラッキングなどの追加機能により、広範なアプリケーションに対して柔軟で使いやすいソリューションを実現できます。軽負荷時の自動周波数フォールドバックと、オプションの外部バイアスにより、負荷範囲の全体にわたって効率が向上します。このファミリは、必要な外付けコンポーネントが少なく、PCBレイアウトが単純になるようピン配置が設計されており、最適なEMIと熱性能を実現しています。保護機能として、サーマル・シャットダウン、入力低電圧誤動作防止、サイクル単位の電流制限、ヒカップ短絡保護機能が搭載されています。LM73605およびLM73606デバイスはピン互換なので、電流を簡単にスケーリングできます。
型番 | パッケージ | 本体サイズ(公称) |
---|---|---|
LM73605 | WQFN (30) ウェッタブル・フランク |
6.00mm×4.00mm |
LM73606 |
日付 | 改訂内容 | 注 |
---|---|---|
2017年9月 | * | 初版 |
PIN | I/O(1) | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1, 2, 3, 4, 5 | SW | P | Switching output of the regulator. Internally connected to source of the HS FET and drain of the LS FET. Connect to power inductor and bootstrap capacitor. |
6 | CBOOT | P | Bootstrap capacitor connection for HS FET driver. Connect a high-quality 470-nF capacitor from this pin to the SW pin. |
7 | VCC | P | Output of internal bias supply. Used as supply to internal control circuits and drivers. Connect a high-quality 2.2-µF capacitor from this pin to GND. TI does not recommend loading this pin by external circuitry. |
8 | BIAS | P | Optional BIAS LDO supply input. TI recommends tying to VOUT when 3.3 V ≤ VOUT ≤ 18 V, or tie to an external 3.3-V or 5-V rail if available, to improve efficiency. BIAS pin voltage must not be greater than VIN. Tie to ground when not in use. |
9 | RT | A | Switching frequency setting pin. Place a resistor from this pin to ground to set the switching frequency. If floating, the default switching frequency is 500 kHz. Do not short to ground. |
10 | SS/TRK | A | Soft-start control pin. Leave this pin floating for a 5-ms internal soft-start ramp. An external capacitor can be connected from this pin to ground to extend the soft start time. A 2-µA current sourced from this pin charges the capacitor to provide the ramp. Connect to external ramp for tracking. Do not short to ground. |
11 | FB | I | Feedback input for output voltage regulation. Connect a resistor divider to set the output voltage. Never short this pin to ground during operation. |
12–15, 27–30 | NC | — | No internal connection. Connect to ground net and copper to improve heat sinking and board-level reliability. |
16 | PGOOD | O | Open drain power-good flag output. Connect to suitable voltage supply through a current limiting resistor. High = VOUT regulation OK, Low = VOUT regulation fault. PGOOD = LOW when EN = low and VIN > 2 V. |
17 | SYNC/MODE | I | Synchronization input and mode setting pin. Do not float. Tie to ground if not used. Tie to ground: auto mode, higher efficiency at light loads; Tie to logic high: forced PWM, constant switching frequency over load; Tie to external clock source: forced PWM, synchronize to the rising edge of the external clock. |
18 | EN | I | Enable input to regulator. Do not float. High = ON, Low = OFF. Can be tied to PVIN. Precision enable input allows adjustable input voltage UVLO using external resistor divider. |
19 | AGND | G | Analog ground. Ground reference for internal circuitry. All electrical parameters are measured with respect to this pin. Connect to system ground on PCB. |
20–22 | PVIN | P | Supply input to internal bias LDO and HS FET. Connect to input supply and input bypass capacitors CIN. CIN must be placed right next to this pin and PGND pins on PCB, and connected with short and wide traces. |
23–26 | PGND | G | Power ground, connected to the source of LS FET internally. Connect to system ground, DAP/EP, AGND, ground side of CIN and COUT on PCB. Path to CIN must be as short as possible |
EP | DAP | G | Low impedance connection to AGND. Connect to system ground on PCB. Major heat dissipation path for the device. Must be used for heat sinking by soldering to ground copper on PCB. Thermal vias are preferred to improve heat dissipation to other layers. |
PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|
Input voltages | PVIN to PGND | –0.3 | 42 | V |
EN to AGND | –0.3 | VIN + 0.3 | ||
FB, RT, SS/TRK to AGND | –0.3 | 5 | ||
PGOOD to AGND | –0.1 | 20 | ||
SYNC to AGND | –0.3 | 5.5 | ||
BIAS to AGND | –0.3 | Lower of (VIN + 0.3) or 20 | ||
AGND to PGND | –0.3 | 0.3 | ||
Output voltages | SW to PGND | –0.3 | VIN + 0.3 | V |
SW to PGND less than 10-ns transients | –3.5 | 42 | ||
CBOOT to SW | –0.3 | 5 | ||
VCC to AGND | –0.3 | 5 | ||
Operating junction temperature, TJ | –40 | 150 | °C | |
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±750 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Input voltages | PVIN to PGND | 3.5 | 36 | V |
EN | 0 | VIN | ||
FB | 0 | 4.5 | ||
PGOOD | 0 | 18 | ||
BIAS input not used | 0 | 0.3 | ||
BIAS input used | 0 | Lower of (VIN + 0.3) or 18 | ||
AGND to PGND | –0.1 | 0.1 | ||
Output voltage | VOUT | 1 | 95% of VIN | V |
Output current | IOUT, LM73605 | 0 | 5 | A |
IOUT, LM73606 | 0 | 6 | A | |
Temperature | Operating junction temperature, TJ | –40 | 125 | °C |
THERMAL METRIC(1) | LM73605/LM73606 | UNIT | |
---|---|---|---|
RNP (WQFN) | |||
30 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 34.3 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 14.6 | °C/W |
RθJB | Junction-to-board thermal resistance | 7.3 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.1 | °C/W |
ψJB | Junction-to-board characterization parameter | 7.1 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 1 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY VOLTAGE (PVIN PINS) | ||||||
VIN | Operating input voltage range | 3.5 | 36 | V | ||
ISD | Shutdown quiescent current; measured at VIN pin(1) | VEN = 0 V TJ = 25℃ |
0.8 | 10 | µA | |
IQ_NONSW | Operating quiescent current from VIN (non-switching) | VEN = 2 V, VFB = 1.5 V, VBIAS = 3.3 V external | 0.6 | 12 | µA | |
ENABLE (EN PIN) | ||||||
VEN_VCC_H | Enable input high level for VCC output | VEN rising | 1.15 | V | ||
VEN_VCC_L | Enable input low level for VCC output | VEN falling | 0.3 | V | ||
VEN_VOUT_H | Enable input high level for VOUT | VEN rising | 1.14 | 1.196 | 1.25 | V |
VEN_VOUT_HYS | Enable input hysteresis for VOUT | VEN falling hysteresis | –100 | mV | ||
ILKG_EN | Enable input leakage current | VEN = 2 V | 1.4 | 200 | nA | |
INTERNAL LDO (VCC PIN, BIAS PIN) | ||||||
VCC | Internal VCC voltage | PWM operation | 3.27 | V | ||
PFM operation | 3.1 | V | ||||
VCC_UVLO | Internal VCC undervoltage lockout | VCC rising | 2.96 | 3.14 | 3.27 | V |
VCC falling hysteresis | –605 | mV | ||||
VBIAS_ON | Input changeover | VBIAS rising | 3.09 | 3.25 | V | |
VBIAS falling hysteresis | –63 | mV | ||||
IBIAS_NONSW | Operating quiescent current from external VBIAS (non-switching) | VEN = 2 V, VFB = 1.5 V, VBIAS = 3.3 V external | 21 | 50 | µA | |
VOLTAGE REFERENCE (FB PIN) | ||||||
VFB | Feedback voltage | PWM mode | 0.987 | 1.006 | 1.017 | V |
ILKG_FB | Input leakage current at FB pin | VFB = 1 V | 0.2 | 60 | nA | |
HIGH SIDE DRIVER (CBOOT PIN) | ||||||
VCBOOT_UVLO | CBOOT - SW undervoltage lockout | 1.6 | 2.2 | 2.7 | V | |
CURRENT LIMITS AND HICCUP | ||||||
IHS_LIMIT | Short-circuit, high-side current limit(2) | LM73605 | 6 | 7.3 | 8.35 | A |
LM73606 | 7.4 | 8.7 | 9.85 | |||
ILS_LIMIT | Low-side current limit(2) | LM73605 | 4.79 | 5.5 | 6.1 | A |
LM73606 | 5.8 | 6.6 | 7.25 | |||
INEG_LIMIT | Negative current limit | LM73605 | –5 | A | ||
LM73606 | –6 | |||||
VHICCUP | Hiccup threshold on FB pin | 0.36 | 0.4 | 0.44 | V | |
IL_ZC | Zero cross-current limit | 0.06 | A | |||
SOFT START (SS/TRK PIN) | ||||||
ISSC | Soft-start charge current | 1.8 | 2 | 2.2 | µA | |
RSSD | Soft-start discharge resistance | UVLO, TSD, OCP, or EN = 0 | 1 | kΩ | ||
POWER GOOD (PGOOD PIN) and OVERVOLTAGE PROTECTION | ||||||
VPGOOD_OV | Power-good overvoltage threshold | % of FB voltage | 106% | 110% | 113% | |
VPGOOD_UV | Power-good undervoltage threshold | % of FB voltage | 86% | 90% | 93% | |
VPGOOD_HYS | Power-good hysteresis | % of FB voltage | 1.2% | |||
VPGOOD_VALID | Minimum input voltage for proper PGOOD function | 50-µA pullup to PGOOD pin, VEN = 0 V, TJ = 25°C | 1.3 | 2 | V | |
RPGOOD | Power-good ON-resistance | VEN = 2.5V | 40 | 100 | Ω | |
VEN = 0 V | 30 | 90 | ||||
MOSFETS | ||||||
RDS_ON_HS (3) | High-side MOSFET ON-resistance | IOUT = 1 A, VBIAS = VOUT = 3.3 V | 53 | 90 | mΩ | |
RDS_ON_LS (3) | Low-side MOSFET ON-resistance | IOUT = 1 A, VBIAS = VOUT = 3.3 V | 31 | 55 | mΩ | |
THERMAL SHUTDOWN | ||||||
TSD (4) | Thermal shutdown threshold | Shutdown threshold | 160 | °C | ||
Recovery threshold | 135 | °C |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
CURRENT LIMITS AND HICCUP | ||||||
NOC (1) | Number of switching cycles before hiccup is tripped | 128 | Cycles | |||
tOC | Overcurrent hiccup retry delay time | 46 | ms | |||
SOFT START (SS/TRK PIN) | ||||||
tSS | Internal soft-start time | CSS = OPEN, from EN rising edge to PGOOD rising edge | 3.5 | 6.3 | ms | |
POWER GOOD (PGOOD PIN) and OVERVOLTAGE PROTECTION | ||||||
tPGOOD_RISE | PGOOD rising edge deglitch delay | 80 | 140 | 200 | µs | |
tPGOOD_FALL | PGOOD falling edge deglitch delay | 80 | 140 | 200 | µs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
PWM LIMITS (SW PINS) | ||||||
tON-MIN | Minimum switch on-time | 60 | 82 | ns | ||
tOFF-MIN | Minimum switch off-time | 70 | 120 | ns | ||
tON-MAX | Maximum switch on-time | HS timeout in dropout | 3 | 6 | 9 | µs |
OSCILLATOR (RT and SYNC PINS) | ||||||
fOSC | Internal oscillator frequency | RT = Open | 440 | 500 | 560 | kHz |
fADJ | Minimum adjustable frequency by RT or SYNC | RT =115 kΩ, 0.1% | 315 | 350 | 385 | kHz |
Maximum adjustable frequency by RT or SYNC | RT = 17.4 kΩ, 0.1% | 1980 | 2200 | 2420 | kHz | |
VSYNC_HIGH | Sync input high level threshold | 2 | V | |||
VSYNC_LOW | Sync input low level threshold | 0.4 | V | |||
VMODE_HIGH | Mode input high level threshold for FPWM | 0.42 | V | |||
VMODE_LOW | Mode input low level threshold for AUTO mode | 0.4 | V | |||
tSYNC_MIN | Sync input minimum ON and OFF-time | 80 | ns |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VFB_PFM | Output voltage offset at no load in auto mode | VIN = 3.8 V to 36 V, VSYNC = 0 V, auto mode IOUT = 0 A | 2% | |||
VDROP | Minimum input to output voltage differential to maintain specified accuracy | VOUT = 5 V, IOUT = 3 A, fSW = 2.2 MHz | 0.4 | V | ||
IQ_SW | Operating quiescent current (switching) | VEN = 3.3 V, IOUT = 0 A, RT = open, VBIAS = VOUT = 3.3 V , RFBT = 1 Meg | 15 | µA | ||
IPEAK_MIN | Minimum inductor peak current | LM73605 : VSYNC = 0, IOUT = 10 mA |
1 | A | ||
LM73606 : VSYNC = 0 V, IOUT = 10 mA |
1.3 | |||||
IBIAS_SW | Operating quiescent current from external VBIAS (switching) | fSW = 500 kHz, IOUT = 1 A | 7 | mA | ||
fSW = 2.2 MHz, IOUT = 1 A | 25 | |||||
DMAX | Maximum switch duty cycle | While in frequency foldback | 97.5% | |||
tDEAD | Dead time between high-side and low-side MOSFETs | 4 | ns |
The LM73605/6 is an easy-to-use synchronous step-down DC-DC converter that operates from a 3.5-V to 36-V supply voltage. It is capable of delivering up to 5-A (LM73605) or 6-A (LM73606) DC load current with exceptional efficiency and thermal performance in a very small solution size.
The LM73605/6 employs fixed-frequency peak current-mode control with configurable auto or FPWM operation mode. Auto mode provides very high efficiency at light loads, and FPWM mode maintains constant switching frequency over entire load range.
The device is internally compensated, which reduces design time and the number of external components. The switching frequency is programmable from 350 kHz to 2.2 MHz by an external resistor. The LM73605/6 can also synchronize to an external clock within the same frequency range. The wide switching frequency range allows the device to be optimized for a wide range of system requirements. It can be optimized for small solution size with higher frequency; or for high efficiency with lower switching frequency. The LM73605/6 has very low quiescent current, which is critical for battery operated systems. It allows for a wide range of voltage conversion ratios due to very small minimum ON-time (tON-MIN) and minimum OFF-time (tOFF-MIN). Automated frequency foldback is employed at very high or low duty cycles to further extend the operating range.
The LM73605/6 also features a power-good (PGOOD) flag, precision enable, internal or adjustable soft start, pre-biased start-up, and output voltage tracking. Protection features include thermal shutdown, undervoltage lockout (UVLO), cycle-by-cycle current limiting, and short-circuit hiccup protection. It provides flexible and easy-to-use solutions for a wide range of applications.
The family requires very few external components and has a pin out designed for simple, optimum PCB layout for enhanced EMI and thermal performance. The LM73605/6 device is available in a 30-pin WQFN leadless package.
The LM73605/6 is a synchronous buck converter with both power MOSFETs integrated in the device. Figure 10 shows a simplified schematic for synchronous and non-synchronous buck converters. The synchronous buck integrates both high-side (HS) and low-side (LS) power MOSFETs. The non-synchronous buck integrates HS MOSFET and works with a discrete power diode as LS rectifier.
A synchronous converter with integrated HS and LS MOSFETs offers benefits such as less design effort, lower external components count, reduced total solution size, higher efficiency at heavier load, easier PCB design, and more control flexibility.
The main advantage of a synchronous converter is that the voltage drop across the LS MOSFET is lower than the voltage drop across the power diode of a non-synchronous converter. Lower voltage drop translates into less power dissipation and higher efficiency. The LM73605/6 integrates HS and LS MOSFETs with very low on-time resistance to improve efficiency. It is especially beneficial when the output voltage is low. Because the LS MOSFET is integrated into the device, at light loads a synchronous converter has the flexibility to operate in either discontinuous or continuous conduction mode.
An integrated LS MOSFET also allows the controller to obtain inductor current information when the LS switch is on. It allows the control loop to make more complex decisions based on HS and LS currents. It allows the LM73605/6 to have peak and valley cycle-by-cycle current limiting for more robust protection.
The LM73605/6 has configurable auto mode or FPWM options.
In auto mode, the device operates in diode emulation mode (DEM) at light loads. In DEM, inductor current stops flowing when it reaches 0 A. This is also referred to as discontinuous conduction mode (DCM). This is the same behavior as the non-synchronous regulator, with higher efficiency. At heavier load, when the inductor current valley is above 0 A, the device operates in continuous conduction mode (CCM), where the switching frequency is fixed and set by RT pin.
In auto mode, the peak inductor current has a minimum limit, IPEAK_MIN, in the LM73605/6. When peak current reaches IPEAK_MIN, the switching frequency reduces to regulate the required load current. Switching frequency lowers when load reduces. This is when the device operates in pulse frequency modulation (PFM). PFM further improves efficiency by reducing switching losses. Light load efficiency is especially important for battery operated systems.
In forced PWM (FPWM) mode, the device operates in CCM regardless of load with the frequency set by RT pin or synchronization input. Inductor current can go negative at light loads. At light loads, the efficiency is lower than auto mode, due to higher conduction losses and switching losses. In FPWM, the device has fixed switching frequency over the entire load range, which is beneficial to noise sensitive applications.
Figure 11 shows the inductor current waveforms in each mode with heavy load, light load, and very light load. The difference between the two modes is at lighter loads where inductor current valley reaches zero.
In CCM, the inductor current peak-to-peak ripple can be estimated by Equation 1:
The average or DC value of the inductor current equals the load current, or output current IOUT, in steady state. Peak inductor current can be calculated by Equation 2
Valley inductor current can be calculated by Equation 3
In auto mode, the CCM to DCM boundary condition is when IVALLEY = 0 A. When ILripple ≥ IPEAK_MIN, the load current at the DCM boundary condition can be found by Equation 4. When the peak-to-peak ripple current is smaller than ILripple ≥ IPEAK-MIN, the PFM boundary will be reached first.
where
In auto mode, the PFM operation boundary condition is when IPEAK = IPEAK_MIN. Frequency foldback occurs when peak current drops to IPEAK_MIN, no matter whether in CCM or DCM operation. When current ripple is small, ILripple < IPEAK_MIN, the peak current reaches IPEAK_MIN when still in CCM. The output current at CCM PFM boundary can be found by Equation 5
where
The current ripple increases with reduced frequency if load reduces. When valley current reaches zero, the frequency continues to fold back with constant peak current and discontinuous current.
In FPWM mode, there is no IPEAK-MIN limit. The peak current is defined by Equation 2 at light loads and heavy loads.
See Frequency Synchronization and Mode Setting for mode setting options in LM73605/6. Mode setting only affects operation at light loads. There is no difference if load current is above the DCM and PFM boundary conditions discussed above.
The LM73605/6 synchronous switched mode voltage regulator employs fixed frequency peak current mode control with advanced features. The fixed switching frequency is controlled by an internal clock. To get accurate DC load regulation, a voltage feedback loop is implemented to generate peak current command. The HS switch is turned on at the rising edge of the clock. As shown in Figure 12, during the HS switch on-time tON, the SW pin voltage VSW swings up to approximately VIN, and the inductor current IL increases with a linear slope. The HS switch is turned off when the inductor current reaches the peak current command. During the HS switch off-time tOFF, the LS switch is turned on. Inductor current discharges through the LS switch, which forces the VSW to swing below ground by the voltage drop across the LS switch. The LS switch is turned off at the next clock cycle, before the HS switch is turned on. The regulation loop adjusts the peak current command to maintain a constant output voltage.
Duty cycle D is defined by the on-time of the HS switch over the switching period:
where
In an ideal buck converter, where losses are ignored, D is proportional to the output voltage and inverse proportional to the input voltage: D = VOUT ⁄ VIN.
When the LM73605/6 is set to operate in auto mode, the LS switch is turned off when its current reaches zero ampere before the next clock cycle comes. Both HS switch and LS switch are off before the HS switch is turned on at the next clock cycle.
The voltage regulation loop in the LM73605/6 regulates the FB pin voltage to be the same as the internal reference voltage. The output voltage of the LM73605/6 is set by a resistor divider to program the ratio from VOUT to VFB. The resistor divider is connected from the output to ground with the mid-point connecting to the FB pin.
The internal voltage reference and feedback loop produce precise voltage regulation over temperature. TI recommends using divider resistors with 1% tolerance or better, and with temperature coefficient of 100 ppm or lower. Typically, RFBT = 10 kΩ to 100 kΩ is recommended. Larger RFBT and RFBB values reduce the quiescent current going through the divider, which help maintain high efficiency at very light load. But larger divider values also make the feedback path more susceptible to noise. If efficiency at very light load is critical in a certain application, RFBT up to 1 MΩ can be used.
RFBB can be calculated by Equation 7:
The minimum programmable VOUT equals VFB, with RFBB open. The maximum VOUT is limited by the maximum duty cycle at a given frequency:
where
Ideally, without frequency foldback, VOUT_MAX = VIN_MIN × DMAX.
Power losses in the circuit reduces the maximum output voltage. The LM73605/6 folds back switching frequency under tOFF_MIN condition to further extend VOUT_MAX. The device maintains output regulation with lower input voltage. The minimum fold-back frequency is limited by the maximum HS on-time, tON_MAX. Maximum output voltage with frequency foldback can be estimated by:
The voltage drops on the HS MOSFET and inductor DCR have been taken into account in Equation 9. The switching losses were not included.
If the resistor divider is not connected properly, the output voltage cannot be regulated because the feedback loop cannot obtain correct output voltage information. If the FB pin is shorted to ground or disconnected, the output voltage is driven close to VIN. The load connected to the output could be damaged under this condition. Do not short FB to ground or leave it open circuit during operation.
The FB pin is a noise sensitive node. It is important to place the resistor divider as close as possible to the FB pin, and route the feedback node with a short and thin trace. The trace connecting VOUT to RFBT can be long, but it must be routed away from the noisy area of the PCB. For more layout recommendations, see Layout.
The LM73605/6 regulates output voltage when the VCC voltage is higher than the undervoltage lock out (UVLO) level, VCC_UVLO, and the EN voltage is higher than VEN_VOUT_H.
The internal LDO output voltage VCC is turned on when the EN voltage is higher than VEN_VCC_H. The precision enable circuitry is also turned on when VCC is above UVLO. Normal operation of the LM73605/6 with regulated output voltage is enabled when the EN voltage is greater than VEN_VOUT_H. When the EN voltage is less than VEN_VCC_L, the device is in shutdown mode. The internal dividers make sure VEN_VOUT_H is always higher than VEN_VCC_H.
The EN pin cannot be left floating. The simplest way to enable the operation of the LM73605/6 is to connect the EN pin to PVIN, which allows self-start-up of the LM73605/6 when VIN rises. Use of a pullup resistor between PVIN and EN pins helps reduce noise coupling from PVIN pin to the EN pin.
Many applications benefit from employing an enable divider to establish a customized system UVLO. This can be used either for sequencing, system timing requirement, or to reduce the occurrence of deep discharge of a battery power source. Figure 14 shows how to use a resistor divider to set a system UVLO level. An external logic output can also be used to drive the EN pin for system sequencing.
With a selected RENT, the RENB can be calculated by:
where
Note that the divider adds to supply quiescent current by VIN / (RENT + RENB). Small RENT and RENB values add more quiescent current loss. However, large divider values make the node more sensitive to noise. RENT in the hundreds of kΩ range is a good starting point.
The LM73605/6 integrates an internal LDO, generating VCC voltage for control circuitry and MOSFET drivers. The VCC pin must have a 1-µF to 4.7-µF bypass capacitor placed as close as possible to the pin and properly grounded. Do not load the VCC pin or short it to ground during operation. Shorting VCC pin to ground during operation may damage the device.
The UVLO on VCC voltage, VCC_UVLO, turns off the regulation when VCC voltage is too low. It prevents the LM73605/6 from operating until the VCC voltage is enough for the internal circuitry. Hysteresis on VCC_UVLO prevents the part from turning off during power up if VIN droops due to input current demands. The LDO generates VCC voltage from one of the two inputs: the supply voltage VIN, or the BIAS input. When BIAS is tied to ground, the LDO input is VIN. When BIAS is tied to a voltage higher than 3.3 V, the LDO input is VBIAS. BIAS voltage must be lower than both VIN and 18 V.
The BIAS input is designed to reduce the LDO power loss. The LDO power loss is:
The higher the difference between the input and output voltages of the LDO, the more loss occurs to supply the same LDO output current. The BIAS input provides an option to supply the LDO with a lower voltage than VIN, to reduce the difference of the input and output voltages of the LDO and reduce power loss. For example, if the LDO current is 10 mA at a certain frequency with VIN = 24 V and VOUT = 5 V. The LDO loss with BIAS tied to ground is equal to 10 mA × (24 V – 3.27 V) = 207.3 mW, while the loss with BIAS tied to VOUT is equal to 10 mA × (5 – 3.27) = 17.3 mW.
The efficiency improvement is more significant at light and mid loads because the LDO loss is a higher percentage in the total loss. The improvements is more significant with higher switching frequency because the LDO current is higher at higher switching frequency. The improvement is more significant when VIN » VOUT because the voltage difference is higher.
Figure 15 and Figure 16 show efficiency improvement with bias tied to VOUT in a VOUT = 5 V and fSW = 2200 kHz application, in auto mode and FPWM mode, respectively.
VOUT = 5 V | fSW = 2200 kHz | Auto Mode |
VOUT = 5 V | fSW = 2200 kHz | FPWM Mode |
TI recommends tying the BIAS pin to VOUT when VOUT is equal to or greater than 3.3 V and no greater than 18 V. Tie the BIAS pin to ground when not in use. A ceramic capacitor, CBIAS, can be used from the BIAS pin to ground for bypassing. If VOUT has high frequency noise or spikes during transients or fault conditions, a resistor (1 to 10 Ω) connected between VOUT to BIAS can be used together with CBIAS for filtering.
The VCC voltage is typically 3.27 V. When the LM73605/6 is operating in PFM mode with frequency foldback, VCC voltage is reduced to 3.1 V (typical) to further decrease the quiescent current and improve efficiency at very light loads. Figure 17 shows an example of VCC voltage change with mode change.
VOUT = 5 V | fSW = 500 kHz | VIN = 12 V |
VCC voltage has an internal undervoltage lockout threshold, VCC_UVLO. When VCC voltage is higher than VCC_UVLO rising threshold, the device is active and in normal operation if VEN > VEN_VOUT_H. If VCC voltage droops below VCC_UVLO falling threshold, the VOUT is shut down.
The LM73605/6 features controlled output voltage ramp during start-up. The soft-start feature reduces inrush current during start-up and improves system performance and reliability.
If the SS/TRK pin is floating, the LM73605/6 starts up following the fixed internal soft-start ramp.
If longer soft-start time is desired, an external capacitor can be added from SS/TRK pin to ground. There is a 2-µA (typical) internal current source, ISSC, to charge the external capacitor. For a desired soft-start time tSS, capacitance of CSS can be found by Equation 12.
where
The FB voltage always follows the lower potential of the internal voltage ramp or the voltage on the SS/TRK pin. Thus, the soft-start time can only be extended longer than the internal soft-start time by connecting CSS. Use CSS to extend soft-start time when there are a large amount of output capacitors, or the output voltage is high, or the output is heavily loaded during start-up.
LM73605/6 is operating in diode emulation mode during start-up regardless of mode setting. The device is capable of starting up into pre-biased output conditions. During start-up, the device sets the minimum inductor current to zero to avoid back charging the input capacitors.
LM73605/6 can track an external voltage ramp applied to the SS/TRK pin, if the ramp is slower than the internal soft-start ramp. The external ramp final voltage after start-up must be greater than 1.5 V to avoid noise interfering with the reference voltage. Figure 18 shows how to use resistor divider to set VOUT to follow an external ramp.
VOUT tracking also provides the option of ramping up faster than the internal start-up ramp. The FB voltage always follows the lower potential of the internal voltage ramp and the voltage on the SS/TRK pin. Figure 19 shows the case when VOUT ramps slower than the internal ramp, while Figure 20 shows when VOUT ramps faster than the internal ramp. If the tracking ramp is delayed after the internal ramp is completed, VFB follows the tracking ramp even if it is faster than the internal ramp. Faster start-up time may result in large inductor current during start-up. Use with special care.
The SS/TRK pin is discharged to ground by an internal pulldown resistor RSSD when the output voltage is shutting down, such as in the event of UVLO, thermal shutdown, hiccup, or VEN = 0. If a large CSS is used, and the time when VEN = 0 V is very short, the CSS may not be fully discharged before the next soft start. Under this condition, the FB voltage follows the internal ramp slew rate until the voltage on CSS is reached, then follow the slew rate defined by CSS.
The internal oscillator frequency is controlled by the impedance on the RT pin. If the RT pin is open circuit, the LM73605/6 operates at its default switching frequency, 500 kHz. The RT pin is not designed to be connected directly to ground. To program the switching frequency by RT resistor, Equation 13, or Figure 21, or Table 1 can be used to find the resistance value.
SWITCHING FREQUENCY fSW (kHz) | RT RESISTANCE (kΩ) |
350 | 115 |
400 | 100 |
500 | 78.7 (or open) |
750 | 52.3 |
1000 | 39.2 |
1500 | 26.1 |
2000 | 19.1 |
2200 | 17.4 |
The choice of switching frequency is usually a compromise between conversion efficiency and the size of the solution. Lower switching frequency has lower switching losses (including gate charge losses, switch transition losses, etc.). It usually results in higher overall efficiency. However, higher switching frequency allows the use of smaller power inductor and output capacitors, hence a more compact design. Lower inductance also helps transient response (higher large signal slew rate of inductor current), and has lower DCR. The optimal switching frequency is usually a trade-off in a given application and thus needs to be determined on a case-by-case basis. Factors that need to be taken into account include input voltage range, output voltage, most frequent load current level(s), external component choices, solution size/cost requirements, efficiency and thermal management requirements.
The choice of switching frequency may also be limited whether an operating condition triggers tON_MIN or tOFF-MIN. Minimum on-time, tON-MIN, is the smallest time that the HS switch can be on. Minimum OFF-time, tOFF-MIN, is the smallest duration that the HS switch can be off.
In CCM operation, tON-MIN and tOFF_MIN limits the voltage conversion range given a selected switching frequency, FSW. The minimum duty cycle allowed is:
The maximum duty cycle allowed is:
Given an output voltage, the choice of the switching frequency affects the allowed input voltage range, solution size and efficiency. The maximum operational supply voltage can be found by:
At lower supply voltage, the switching frequency decreases once tOFF-MIN is tripped. The minimum VIN without frequency foldback can be approximated by:
With a desired VOUT, the range of allowed VIN is narrower with higher switching frequency.
LM73605/6 has an advanced frequency fold-back algorithm under both tON_MIN and tOFF_MIN conditions. With frequency foldback, stable output voltage regulation is extended to wider range of supply voltages.
At very high VIN conditions, where tON_MIN limitation is met, the switching frequency reduces to allow higher VIN while maintaining VOUT regulation. Note that the peak to peak inductor current ripple will increase with higher VIN and lower frequency. TI does not recommend designing the circuit to operate with tON_MIN under typical conditions.
At very low VIN conditions, where tOFF_MIN limitation is met, the switching frequency decreases until tON_MAX condition is met. Such frequency fold-back mechanism allows the LM73605/6 to have very low dropout voltage regardless of frequency setting.
The LM73605/6 switching action can synchronize to an external clock from 350 kHz to 2.2 MHz. TI recommends connecting the external clock to the SYNC/MODE pin with an appropriate termination resistor. Ground the SYNC/MODE pin if not used.
Recommendations for the external clock include a high level no lower than 2 V, low level no higher than 0.4 V, duty cycle between 10% and 90%, and both positive and negative pulse width no shorter than 80 ns. When the external clock fails at logic high or low, the LM73605/6 switches at the frequency programmed by the RT resistor after a time-out period. TI recommends connecting a resistor to the RT pin such that the internal oscillator frequency is the same as the external clock frequency. This allows the regulator to continue operating at approximately the same switching frequency if the external clock fails with the same control loop behavior.
The SYNC/MODE pin is also used as an operation mode control input.
SYNC/MODE INPUT | SWITCHING FREQUENCY | OPERATING MODE | LIGHT LOAD BEHAVIOR |
Logic low | Set by RT resistor | Auto mode |
|
Logic high | Set by RT resistor | FPWM mode |
|
External clock | Set by external clock |
The LM73605/6 is internally compensated. The internal compensation is designed such that the loop response is stable over a wide operating frequency and output voltage range. The internal R-C values are 500 kΩ and 30 pF respectively.
When large resistance value (MΩ) is used for RFBT, the pole formed by an internal parasitic capacitor and RFBT can be low enough to reduce the phase margin. If only low ESR output capacitors (ceramic types) are used for COUT, the control loop could have low phase margin. To provide a phase boost an external feed-forward capacitor (CFF) can be added in parallel with RFBT. Choose the CFF capacitor to provide most phase boost at the estimated crossover frequency fX:
where
Select COUT so that the fX is no higher than 1/6 of the switching frequency. Typically, fX / fSW = 1/10 to 1/8 provides a good combination of stability and performance.
Place the external feed-forward capacitor in parallel with the top resistor divider RFBT when additional phase boost is needed.
The feed-forward capacitor CFF in parallel with RFBT places an additional zero before the crossover frequency of the control loop to boost phase margin. The zero frequency can be found by Equation 19:
An additional pole is also introduced with CFF at the frequency of:
Select the CFF so that the bandwidth of the control loop without the CFF is centered between fZ-CFF and fP-CFF. The zero at fZ-CFF adds phase boost at the crossover frequency and improves transient response. The pole at fP-CFF helps maintaining proper gain margin at frequency beyond the crossover.
The need of CFF depends on RFBT and COUT. Typically, choose RFBT ≤ 100 kΩ. CFF may not be required, because the internal parasitic pole is at higher frequency. If COUT has larger ESR, and ESR zero fZ-ESR = 1 / (2π × ESR × COUT) is low enough to provide phase boost around the crossover frequency, do not use CFF. Equation 21 was tested for ceramic output capacitors:
The CFF creates a time constant with RFBT that couples in the attenuated output voltage ripple to the FB node. If the CFF value is too large, it can couple too much ripple to the FB and affect VOUT regulation. It could also couple too much transient voltage deviation and falsely trigger PGOOD flag.
The driver of the HS switch requires a bias voltage higher than the VIN voltage. The capacitor, CBOOT in 概略回路図, connected between CBOOT and SW pins works as a charge pump to boost voltage on the CBOOT pin to (VSW + VCC). A boot diode is integrated on the die to minimize external component count. TI recommends a high-quality 0.47-µF, 6.3-V or higher voltage ceramic capacitor for CBOOT. The VBOOT_UVLO threshold is designed to maintain proper HS switch operation. If the CBOOT is not charged above this voltage with respect to SW, the device initiates a charging sequence using the LS switch before turning on the HS switch.
The LM73605/6 has a built-in power-good (PGOOD) flag to indicate whether the output voltage is at an appropriate level or not. The PGOOD flag can be used for start-up sequencing of multiple rails. The PGOOD pin is an open-drain output that requires a pullup resistor to an appropriate logic voltage (any voltage below 15 V). The pin can sink 5 mA of current and maintain its specified logic low level. A typical pullup resistor value is 10 kΩ to 100 kΩ. When the FB voltage is higher than VPGOOD-OV or lower than VPGOOD-UV threshold, the PGOOD internal switch is turned on, and the PGOOD pin voltage is pulled low. When the FB is within the range, the PGOOD switch is turned off, and the pin is pulled up to the voltage connected to the pullup resistor. The PGOOD function also have a deglitch timer for about 140 µs for each transition. If it is desired to pull up PGOOD pin to a voltage higher than 15 V, a resistor divider can be used to divide the voltage down.
With a given pullup voltage VPU, select a desired voltage on the PGOOD pin, VPG. With a selected RPGT, the RPGB can be found by:
When the device is disabled, the output voltage is low, and the PGOOD flag indicates logic low as long as VIN > 2 V.
The LM73605/6 is protected from overcurrent conditions with cycle-by-cycle current limiting on both HS and LS MOSFETs.
The HS switch is turned off when HS current goes beyond the peak current limit, IHS-LIMIT. The LS switch can only be turned off when LS current is below LS current limit, ILS-LIMIT. If the LS switch current is higher than ILS-LIMIT at the end of a switching cycle, the switching cycle is extended until the LS current reduces below the limit.
Current limiting on both HS and LS switches provides tighter control of the maximum DC inductor current, or output current. They also help prevent runaway current at extreme conditions. With LM73605/6, the maximum output current is always limited at
The LM73605/6 employs hiccup current protection at extreme overload conditions, including short-circuit condition. Hiccup is only activated when VOUT droops below 40% (typical) of the regulation voltage and stays below for 128 consecutive switching cycles. Under overcurrent conditions when VOUT has not fallen below 40% of regulation, the LM73605/6 continues operation with cycle-by-cycle HS and LS current limiting.
Hiccup is disabled during soft-start. When hiccup is triggered, the device turns off VOUT regulation and re-tries soft start after a re-try delay time, TOC = 46 ms (typical). The long wait time allows the device, and the load, to cool down under such fault conditions. If the fault condition still exists when re-try, hiccup shuts down the device and repeats the wait and re-try cycle. If the fault condition has been removed, the device starts up normally.
If tracking was used for initial sequencing, the device restarts using the internal soft-start ramp. Hiccup mode helps to reduce the device power dissipation and die temperature under severe overcurrent conditions and short circuits. It improves system reliability and prolongs the life span of the device.
In FPWM mode, negative current protection is implemented to protect the switches from extreme negative currents. When LS switch current reaches INEG-LIMIT, LS switch turns off, and HS switch turns on to conduct the negative current. HS switch is turned off once its current reaches 0 A.
Thermal shutdown protection prevents the device from extreme junction temperature. The device is turned off when the junction temperature exceeds 160°C (typical). After thermal shutdown occurs, hysteresis prevents the device from switching until the junction temperature drops to approximately 135°C. When the junction temperature falls below 135°C, the LM73605/6 restarts.
The EN pin provides electrical on/off control of the device. When the EN pin voltage is below VEN_VCC_L, the device is in shutdown mode. The LDO output voltage VCC = 0 V and the output voltage VOUT = 0 V. In shutdown mode the quiescent current drops to a very low value.
The internal LDO has a lower EN threshold than that required to start the regulator. When the EN pin voltage is above VEN_VCC_H, the internal LDO regulates the VCC voltage. The precision enable circuitry is turned on once VCC is above VCC_UVLO. The device is in standby mode if EN voltage is below VEN_VOUT_H. The internal MOSFETs remains in tri-state unless the voltage on EN pin goes beyond VEN_VOUT_H threshold. The LM73605/6 also employs UVLO protection. If the VCC voltage is below the VCC_UVLO level, the output of the regulator is turned off.
The LM73605/6 is in active mode when the EN voltage is above VEN_VOUT_H, and VCC is above VCC_UVLO. The simplest way to enable the operation of the LM73605/6 is to pull up the EN pin to PVIN, which allows self-start-up when the input voltage ramps up.
In active mode, depending on the load current and mode setting, the LM73605/6 is in one of four modes:
See Table 2 for mode-setting details.
In CCM operation, inductor current has a continuous triangular waveform. The HS switch is on at the beginning of a switching cycle and the LS switch is turned off the end of each switching cycle. In auto mode, the LM73605/6 operates in CCM when the load current is higher than ½ of the peak-to-peak inductor current (ILripple). In FPWM mode, the LM73605/6 operates in CCM regardless of load.
In CCM operation, the switching frequency is typically constant, unless tON-MIN, tOFF-MIN, or IPEAK-MIN conditions are met. The constant switching frequency is determined by RT pin setting, or the external synchronization clock frequency. The duty cycle is also constant in CCM: D = VOUT / VIN if loss is ignored, regardless of load. The peak-to-peak inductor ripple is constant with the same VIN and VOUT, regardless of load.
With very high or very low supply voltages, when the tON-MIN or tOFF-MIN condition is met, the frequency reduces to maintain VOUT regulation with even higher or lower VIN, respectively. When the IPEAK_MIN condition is met in auto mode, switching frequency will fold back to provide higher efficiency. IPEAK_MIN is disabled in FPWM mode.
DCM operation only happens in auto mode, when the load current is lower than half of the CCM inductor current ripple, and peak current is higher than IPEAK-MIN. There is no DCM in FPWM mode. DCM is also known as diode emulation mode. The LS FET is turned off when the inductor current ramps to 0 A. DCM has the same switching frequency as CCM, which is set by the RT pin. Duty cycle and peak current reduces with lighter load in DCM. DCM is more efficient than FPWM under the same condition, because of lower switching losses and lower conduction losses. When the peak current reduces to IPEAK_MIN at lighter load, the LM73605/6 operates in PFM mode.
Pulse-frequency-modulation (PFM) mode is activated when peak current is lower than IPEAK-MIN, only in auto mode. Peak current is kept constant and VOUT is regulated by frequency. Efficiency is greatly improved by lowered switching losses, especially at very light loads.
In PFM operation, a small DC positive offset appears on VOUT. The lower the frequency is folded back in PFM, the more the DC offset is on VOUT. See VOUT regulation curves in Application Curves. If the DC offset on VOUT is not acceptable, a dummy load at VOUT, or lower RFBT and RFBB resistance values can be used to reduce the offset. Alternatively the device can be run in FPWM mode where the switching frequency is constant, and no offset is added to affect the VOUT accuracy unless tON_MIN is reached.
The LM73605/6 has hiccup current protection at extreme overload and short circuit conditions. Hiccup is activated when VOUT droops below 40% (typical) of the regulation voltage and stays for 128 consecutive switching cycles. Hiccup is disabled during soft start. In hiccup, the device turns off VOUT and re-tries soft start after 46-ms wait time. Cycle repeats until overcurrent fault condition has been removed. Hiccup mode helps to reduce the device power dissipation and die temperature under severe overcurrent conditions and short circuits. It improves system reliability and prolongs the life span of the device.
Under overcurrent conditions when VOUT droops below regulation but above 40% of regulated voltage, the LM73605/6 stays in cycle-by-cycle HS and LS current limiting protection mode.
Thermal shutdown prevents the device from extreme junction temperature by turning off the device when the junction temperature exceeds 160°C (typical). After thermal shutdown occurs, hysteresis prevents the device from switching until the junction temperature drops to approximately 135°C. When the junction temperature falls below 135°C, the LM73605/6 restarts.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The LM73605/6 device is a step-down DC-DC voltage regulator. It is designed to operate with a wide supply voltage range (3.5 V to 36 V), wide switching frequency range (350 kHz to 2.2 MHz), and wide output voltage range: up to 95% VIN. is a synchronous converter with both HS and LS MOSFETs integrated, and it is capable of delivering a maximum output current of 5 A (LM73605) or 6 A (LM73606). The following design procedure can be used to select component values for the LM73605/6. Alternately, the WEBENCH® software may be used to generate a complete design. The WEBENCH® software uses an iterative design procedure and accesses a comprehensive database of components when generating a design (see Custom Design With WEBENCH® Tools). This section presents a simplified discussion of the design process.
The LM73605/6 only requires a few external components to perform high-efficiency power conversion, as shown in Simplified Schematic.
The LM73605/6 also integrates many practical features to meet a wide range of system design requirements and optimization, such as UVLO, programmable soft-start time, start-up tracking, programmable switching frequency, clock synchronization and a power-good flag. Note that for ease of use, the feature pins do not require an additional component when not in use. They can be either left floating or shorted to ground. Please refer to Pin Configuration and Functions for details.
A comprehensive schematic with all features utilized is shown in Figure 26.
The external components must fulfill not only the needs of the power conversion, but also the stability criteria of the control loop. The LM73605/6 is optimized to work with a range of external components. For quick component selection, Table 3 can be used.
fSW (kHz) | VOUT (V) | L (µH) | COUT (µF)(1) | RFBT (kΩ) | RFBB (kΩ) | RT (kΩ) |
350 | 1 | 2.2 | 500 | 100 | OPEN | 115 |
500 | 1 | 1.5 | 400 | 100 | OPEN | 78.7 or open |
1000 | 1 | 0.68 | 200 | 100 | OPEN | 39.2 |
2200 | 1 | 0.47 | 100 | 100 | OPEN | 17.4 |
350 | 3.3 | 4.7 | 200 | 100 | 43.5 | 115 |
500 | 3.3 | 3.3 | 150 | 100 | 43.5 | 78.7 or open |
1000 | 3.3 | 1.8 | 88 | 100 | 43.5 | 39.2 |
2200 | 3.3 | 1.2 | 44 | 100 | 43.5 | 17.4 |
350 | 5 | 6.8 | 120 | 100 | 25 | 115 |
500 | 5 | 4.7 | 88 | 100 | 25 | 78.7 or open |
1000 | 5 | 3.3 | 66 | 100 | 25 | 39.2 |
2200 | 5 | 2.2 | 44 | 100 | 25 | 17.4 |
350 | 12 | 15 | 66 | 100 | 9.1 | 115 |
500 | 12 | 10 | 44 | 100 | 9.1 | 78.7 or open |
1000 | 12 | 6.8 | 22 | 100 | 9.1 | 39.2 |
350 | 24 | 22 | 40 | 100 | 4.3 | 115 |
500 | 24 | 15 | 30 | 100 | 4.3 | 78.7 or open |
Detailed design procedure is described based on a design example. For this design example, use the parameters listed in Table 4.
DESIGN PARAMETER | VALUE |
Typical input voltage | 12 V |
Output voltage | 5 V |
Output current | 5 A |
Operating frequency | 500 kHz |
Soft-start time | 11 ms |
To create a custom design with the WEBENCH® Power Designer, click the LM73605 or LM73606 device.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability.
In most cases, these actions are available:
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
The output voltage of the LM73605/6 device is externally adjustable using a resistor divider network. The divider network is comprised of top feedback resistor RFBT and bottom feedback resistor RFBB. Use Equation 24 to determine the output voltage of the converter.
Typically, RFBT = 10 kΩ to 100 kΩ is recommended. Larger RFBT and RFBB values reduce the quiescent current going through the divider, which help maintain high efficiency at very light loads. But larger divider values also make the feedback path more susceptible to noise. If efficiency at very light loads is critical in a certain application, RFBT up to 1 MΩ can be used.
RFBT = 100 kΩ is selected here. RFBB = 24.99 kΩ can be calculated to get 5-V output voltage.
The default switching frequency of the LM73605/6 device is set at 500 kHz. For this design, the RT pin can be floating, and the LM73605/6 switches at 500 kHz in CCM mode. An RT resistor of 78.7 kΩ, calculated using Equation 13, Figure 21, or Table 1, can be connected from RT pin to ground to obtain 500-kHz operation frequency as well.
The LM73605/6 switching action can synchronize to an external clock from 350 kHz to 2.2 MHz. TI recommends connecting an external clock to the SYNC/MODE pin with a 50-Ω to 100-Ω termination resistor. The SYNC/MODE pin must be grounded if not used.
RT pin is floating and SYNC/MODE pin is tied to ground in this design.
The LM73605/6 device requires high-frequency ceramic input decoupling capacitors. Depending on the application, a bulk input capacitor can also be added. The typical recommended ceramic decoupling capacitors include one small, 0.1 µF to 1 µF, and one large, 10 µF to 22 µF, capacitors. TI recommends high-quality ceramic type X5R or X7R capacitors. The voltage rating must be greater than the maximum input voltage. As a general rule, to compensate the derating TI recommends a voltage rating of twice the maximum input voltage.
It is very important in buck regulator to place the small decoupling capacitor right next to the PVIN and PGND pins. This capacitor is used to bypass the high frequency switching noise by providing a return path of the noise. It prevents the noise from spreading to wider area of the board. The large bypass ceramic capacitor must also be as close as possible to the PVIN and PGND pins.
Additionally, some bulk capacitance may be required, especially if the LM73605/6 circuit is not located within approximately 2 inches from the input voltage source. This capacitor is used to provide damping to the voltage spike due to the lead inductance of the cable. The optimum value for this capacitor is four times the ceramic input capacitance with ESR close to the characteristic impedance of the LC filter formed by your input inductance and your ceramic input capacitors. It is not critical that the electrolytic filter be at the optimum value for damping, but it must be rated to handle the maximum input voltage including ripple voltage.
For this design, two 10-µF, X7R dielectric capacitors rated for 50 V are used for the input decoupling capacitance, and a capacitor with a value of 0.47 µF for high-frequency filtering.
NOTE
DC bias effect: High capacitance ceramic capacitors have a DC bias derating effect, which will have a strong influence on the final effective capacitance. Therefore, the right capacitor value has to be chosen carefully. Package size and voltage rating in combination with dielectric material are responsible for differences between the rated capacitor value and the effective capacitance.
The first criterion for selecting an output inductor is the inductance. In most buck converters, this value is based on the desired peak-to-peak ripple current in the inductor, ILripple. An inductance that gives a ripple current of 10% to 30% of the maximum output current (5 A or 6 A) is a good starting point. The inductance can be calculated from Equation 26:
where
Selected ILripple is between 10% to 30% of the rated current of the device.
As with switching frequency, the selection of the inductor is a tradeoff between size, cost, and performance. Higher inductance gives lower ripple current and hence lower output voltage ripple. With peak current mode control, the current ripple is the input signal to the control loop. A certain amount of ripple current is needed to maintain the signal-to-noise ratio of the control loop. Within the same series (same size/height), a larger inductance will have a higher series resistance (ESR). With similar ESR, size and/or height will be greater. Larger inductance also has slower current slew rate during large load transients.
Lower inductance usually results in a smaller, less expensive component; however, the current ripple will be higher, thus more output capacitor is needed to maintain the same amount of output voltage ripple. The RMS current is higher with the same load current due to larger ripple. The switching loss is higher because the switch current, which is the peak current, is higher when the HS switch turns off and LS switch turns on. Core loss of the inductor is also larger with higher ripple. Core loss needs to be considered, especially with higher switching frequencies. Check the ripple current over VIN_MIN to VIN_MAX range to make sure current ripple is reasonable over entire supply voltage range.
For applications with large VOUT and typical VOUT / VIN > 50%, sub-harmonic oscillation can be a concern in peak current-mode-controlled buck converters. Select inductance so that
where
The second criterion is inductor saturation current rating. Because the maximum inductor current is limited by the high-side switch current limit, it is advised to select an inductor with a saturation current higher than the ILIMIT-HS. TI recommends selection of soft saturation inductors. A power inductor could be the major source of radiated noise. When EMI is a concern in the application, select a shielded inductor, if possible.
For this design, 20% ripple of 5 A yields 5.8-µH inductance. A 4.7-µH inductor is selected, which gives 25% ripple current.
The output capacitor is responsible for filtering the inductor current, and supplying load current during transients. Capacitor selection depends on application conditions as well as ripple and transient requirements. Best performance is achieved by using ceramic capacitors or combinations of ceramic and other types of capacitors. For high output voltage conditions, such as 12 V and above, finding ceramic capacitors that are rated for an appropriate voltage becomes challenging. In such cases choose a low-ESR SP-CAP™ or POSCAP™-type capacitor. It is a good idea to use a low-value ceramic capacitor in parallel with other capacitors, to bypass high frequency noise between ground and VOUT.
For a given input and output requirement, Equation 28 gives an approximation for a minimum output capacitor required.
where
Along with Equation 28, for the same requirement calculate the maximum ESR with Equation 29.
The output capacitor is also the dominating factor in the loop response of a peak-current mode controlled buck converter. A simplified estimation of the control loop crossover frequency can be found by Equation 18.
Select COUT so that the fX is no higher than 1/6 of the switching frequency. Typically, fX / fSW = 1/10 to 1/8 provides a good combination of stability and performance.
For this design, one 0.47-µF, 50-V X7R and four 22-µF, 16-V, X7R ceramic capacitors are used in parallel.
The LM73605/6 is internally compensated. Typically, select RFBT ≤ 100 kΩ, then CFF is not needed. When very low quiescent current is needed, RFBT = 1 MΩ may be used. If COUT is mainly ceramic type low ESR capacitors, an external feed-forward capacitor CFF may be needed to improve the phase margin. Add CFF in parallel with RFBT. CFF is chosen such that the phase boost is maximized at the estimated crossover frequency fX. Equation 21 was tested.
With this design, because RFBT = 100 kΩ is selected, no CFF is needed.
Every LM73605/6 design requires a bootstrap capacitor, CBOOT. The recommended bootstrap capacitor is 0.47 µF and rated at 6.3 V or greater. The bootstrap capacitor is located between the SW pin and the CBOOT pin. The bootstrap capacitor must be a high-quality ceramic type with X7R or X5R grade dielectric for temperature stability.
The VCC pin is the output of an internal LDO for LM73605/6. The input for this LDO comes from either VIN or BIAS pin voltage. The recommended CVCC capacitor is 2.2 µF and rated at 6.3 V or greater. It must be a high-quality ceramic type with X7R or X5R grade to insure stability. Never short VCC pin to ground during operation.
Because VOUT = 5 V in this design, the BIAS pin is tied to VOUT to reduce LDO power loss. The output voltage is supplying the LDO current instead of the input voltage. The power saving is ILDO × (VIN – VOUT). The power saving is more significant when VIN >> VOUT and with higher frequency operation. To prevent VOUT noise and transients from coupling to BIAS, a series resistor, 1 Ω to 10 Ω, may be added between VOUT and BIAS. A bypass capacitor with a value of 1 μF or higher can be added close to the BIAS pin to filter noise.
The SS/TRK pin can be floating to start up following the internal soft-start ramp. In order to extend the soft-start time, an external soft-start capacitor can be used. Use Equation 12 in order to calculate the soft-start capacitor value.
With a desired soft-start time tSS = 11 ms, a soft-start charging current of ISSC = 2 µA (typical), and VFB = 1.006 V (typical), Equation 12 yields a soft-start capacitor value of 22 nF.
The system undervoltage lockout (UVLO) is adjusted using the external voltage divider network of RENT and RENB. With one selected RENT value, RENB can be found by Equation 10.
Note that the divider adds to supply quiescent current by VIN / (RENT + RENB). Small RENT and RENB values add more quiescent current loss. However, large divider values make the node more sensitive to noise.
In this design, EN pin is tied to PVIN pin with a 100-kΩ resistor.
For this design, a 100-kΩ resistor is used to pull up PGOOD to VOUT.
VOUT = 3.3 V | fSW = 500 kHz | Auto Mode |
VOUT = 3.3 V | fSW = 2200 kHz | Auto Mode |
VOUT = 3.3 V | fSW = 350 kHz | Auto Mode |
VOUT = 5 V | fSW = 500 kHz | Auto Mode |
VOUT = 5 V | fSW = 1000 kHz | Auto Mode |
VOUT = 5 V | fSW = 2200 kHz | Auto Mode |
VOUT = 12 V | fSW = 500 kHz | Auto Mode |
VOUT = 5 V | fSW = 500 kHz | Auto Mode |
VOUT = 5 V | fSW = 2200 kHz | Auto Mode |
VOUT = 3.3 V | fSW = 2200 kHz | Auto Mode |
VOUT = 3.3 V | fSW = 500 kHz | Auto Mode |
VOUT = 12 V | fSW = 500 kHz | Auto Mode |
VOUT = 5 V | fSW = 2200 kHz | Auto Mode |
VOUT = 5 V | fSW = 500 kHz | Auto Mode |
VOUT = 3.3 V | fSW = 500 kHz | Auto Mode |
VIN = 12 V | VOUT = 3.3 V | fSW = 500 kHz |
IOUT = 1 mA | Auto Mode |
VIN = 12 V | VOUT = 3.3 V | fSW = 500 kHz |
IOUT = 100 mA | Auto Mode |
VIN = 12 V | VOUT = 3.3 V | fSW = 500 kHz |
IOUT = 6 A | Auto Mode |
VIN = 12 V | VOUT set at 3.3 V | fSW set at 500 kHz |
IOUT = 7.5 A | VOUT droops to 2 V |
VIN = 12 V | VOUT = 3.3 V | fSW = 500 kHz |
IOUT= 200 mA | FPWM Mode |
VIN = 12 V | VOUT = 3.3 V | fSW = 500 kHz |
IOUT = 5 A | Auto Mode |
VIN = 12 V | VOUT = 3.3 V | fSW = 500 kHz |
IOUT = 10 mA to 6 A to 10 mA | Auto Mode |
VIN = 12 V | VOUT = 5 V | fSW = 2200 kHz |
IOUT = 10 mA to 5 A to 10 mA | Auto Mode |
IOUT = 100 mA | VOUT = 3.3 V | fSW = 500 kHz |
VIN = 10 V to 35 V to 10 V | Auto Mode |
VOUT = 3.3 V | fSW = 500 kHz | FPWM Mode |
VOUT = 3.3 V | fSW = 2200 kHz | FPWM Mode |
VOUT = 3.3 V | fSW = 1000 kHz | Auto Mode |
VOUT = 5 V | fSW = 500 kHz | FPWM Mode |
VOUT = 5 V | fSW = 1000 kHz | FPWM Mode |
VOUT = 5 V | fSW = 2200 kHz | FPWM Mode |
VOUT = 12 V | fSW = 500 kHz | FPWM Mode |
VOUT = 5 V | fSW = 500 kHz | FPWM Mode |
VOUT = 5 V | fSW = 2200 kHz | FPWM Mode |
VOUT = 3.3 V | fSW = 2200 kHz | FPWM Mode |
VOUT = 3.3 V | fSW = 1000 kHz | Auto Mode |
VOUT = 12 V | fSW = 500 kHz | FPWM Mode |
VOUT = 5 V | fSW = 2200 kHz | FPWM Mode |
VOUT = 5 V | fSW = 1000 kHz | Auto Mode |
VOUT = 12 V | fSW = 500 kHz | Auto Mode |
VIN = 12 V | VOUT = 3.3 V | fSW = 500 kHz |
IOUT = 1 mA | FPWM Mode |
VIN = 12 V | VOUT = 3.3 V | fSW = 500 kHz |
IOUT = 100 mA | FPWM Mode |
VIN = 3.66 V | VOUT = 3.3 V | fSW set at 500 kHz |
IOUT = 3 A | Auto Mode |
VIN = 12 V | VOUT = 3.3 V | fSW = 500 kHz |
VIN = 12 V | VOUT = 3.3 V | fSW = 500 kHz |
IOUT= 200 mA | Auto Mode |
VIN = 12 V | VOUT = 3.3 V | fSW = 500 kHz |
VPRE-BIAS= 1.5 V | Auto Mode |
VIN = 12 V | VOUT = 3.3 V | fSW = 500 kHz |
IOUT = 10 mA to 6 A to 10 mA | FPWM Mode |
VIN = 12 V | VOUT = 5 V | fSW = 2200 kHz |
IOUT = 10 mA to 5 A to 10 mA | FPWM Mode |
IOUT = 2 A | VOUT = 3.3 V | fSW = 500 kHz |
VIN = 10 V to 35 V to 10 V | Auto Mode |