8.1.1 Input Capacitor

The LP2996A does not require a capacitor for input stability, but it is recommended for improved performance during large load transients to prevent the input rail from dropping. The input capacitor should be located as close as possible to the PVIN pin. Several recommendations exist dependent on the application required. A typical value recommended for AL electrolytic capacitors is 50 µF. Ceramic capacitors can also be used, a value in the range of 10 µF with X5R or better would be an ideal choice. The input capacitance can be reduced if the LP2996A is placed close to the bulk capacitance from the output of the 2.5 V DC-DC converter. If the two supply rails (AVIN and PVIN) are separated then the 47 uF capacitor should be placed as close to possible to the PVIN rail. An additional 0.1 uF ceramic capacitor can be placed on the AVIN rail to prevent excessive noise from coupling into the device.

8.1.2 Output Capacitor

The LP2996A has been designed to be insensitive of output capacitor size or ESR (Equivalent Series Resistance). This allows the flexibility to use any capacitor desired. The choice for output capacitor will be determined solely on the application and the requirements for load transient response of V_TT. As a general recommendation the output capacitor should be sized above 100 µF with a low ESR for SSTL applications with DDR-SDRAM. The value of ESR should be determined by the maximum current spikes expected and the extent at which the output voltage is allowed to droop. Several capacitor options are available on the market and a few of these are highlighted below:

AL - It should be noted that many aluminum electrolytics only specify impedance at a frequency of 120 Hz, which indicates they have poor high frequency performance. Only aluminum electrolytics that have an impedance specified at a higher frequency (between 20 kHz and 100 kHz) should be used for the LP2996A. To improve the ESR several AL electrolytics can be combined in parallel for an overall reduction. An important note to be aware of is the extent at which the ESR will change over temperature. Aluminum electrolytic capacitors can have their ESR rapidly increase at cold temperatures.

Ceramic - Ceramic capacitors typically have a low capacitance, in the range of 10 to 100 µF range, but they have excellent AC performance for bypassing noise because of very low ESR (typically less than 10 mΩ). However, some dielectric types do not have good capacitance characteristics as a function of voltage and temperature. Because of the typically low value of capacitance it is recommended to use ceramic capacitors in parallel with another capacitor such as an aluminum electrolytic. A dielectric of X5R or better is recommended for all ceramic capacitors.

Hybrid - Several hybrid capacitors such as OS-CON and SP are available from several manufacturers. These offer a large capacitance while maintaining a low ESR. These are the best solution when size and performance are critical, although their cost is typically higher than any other capacitor.

8.1.3 Thermal Dissipation

Since the LP2996A is a linear regulator any current flow from V_TT will result in internal power dissipation generating heat. To prevent damaging the part from exceeding the maximum allowable junction temperature, care should be taken to derate the part dependent on the maximum expected ambient temperature and power dissipation. The maximum allowable internal temperature rise (T_Rmax) can be calculated given the maximum ambient temperature (T_Amax) of the application and the maximum allowable junction temperature (T_Jmax).

From this equation, the maximum power dissipation (P_Dmax) of the part can be calculated:

The θ_JA of the LP2996A will be dependent on several variables: the package used; the thickness of copper; the number of vias and the airflow.

Figure 17. Θ_JA vs Airflow

Additional improvements can be made by the judicious use of vias to connect the part and dissipate heat to an internal ground plane. Using larger traces and more copper on the top side of the board can also help. With careful layout it is possible to reduce the θ_JA further than the nominal values shown in Figure 17.

Layout is also extremely critical to maximize the output current with the SO PowerPAD package. By simply placing vias under the DAP the θ_JA can be lowered significantly.

Additional improvements in lowering the θ_JA can also be achieved with a constant airflow across the package. Maintaining the same conditions as above and utilizing the 2x2 via array, Figure 18 shows how the θ_JA varies with airflow.

Figure 18. Θ_JA vs Airflow Speed (Jedec Board with 4 Vias)

Optimizing the θ_JA and placing the LP2996A in a section of a board exposed to lower ambient temperature allows the part to operate with higher power dissipation. The internal power dissipation can be calculated by summing the three main sources of loss: output current at V_TT, either sinking or sourcing, and quiescent current at AVIN and VDDQ. During the active state (when shutdown is not held low) the total internal power dissipation can be calculated from the following equations:

To calculate the maximum power dissipation at V_TT both conditions at V_TT need to be examined, sinking and sourcing current. Although only one equation will add into the total, V_TT cannot source and sink current simultaneously.

The power dissipation of the LP2996A can also be calculated during the shutdown state. During this condition the output V_TT will tri-state, therefore that term in the power equation will disappear as it cannot sink or source any current (leakage is negligible). The only losses during shutdown will be the reduced quiescent current at AVIN and the constant impedance that is seen at the VDDQ pin.

8.2.1 Typical Application Circuit

Figure 19. Typical Application Circuit

8.2.2 DDR-III Applications

With the separate VDDQ pin and an internal resistor divider it is possible to use the LP2996A in applications utilizing DDR-III memory. The output stage is connected to the 1.5 V rail and the AVIN pin can be connected to a 2.2 V - 5.5 V rail.

Figure 20. Recommended DDR-III Termination

If it is not desirable to use the 1.5 V - 2.5 V rail it is possible to connect the output stage to a 3.3 V rail. Care should be taken to not exceed the maximum junction temperature as the thermal dissipation increases with lower V_TT output voltages. For this reason it is not recommended to power PVIN off a rail higher than the nominal 3.3 V. The advantage of this configuration is that it has the ability to source and sink a higher maximum continuous current.

8.2.3 DDR-II Applications

With the separate VDDQ pin and an internal resistor divider it is possible to use the LP2996A in applications utilizing DDR-II memory. Figure 24 and Figure 25 show several implementations of recommended circuits with output curves displayed in the Typical Performance Characteristics. Figure 24 shows the recommended circuit configuration for DDR-II applications. The output stage is connected to the 1.8 V rail and the AVIN pin can be connected to either a 3.3 V or 5 V rail. For DDR-III and DDR-III low power designs in wider temperature applications, the LP2998/Q is recommended.

Figure 21. Recommended DDR-II Termination

If it is not desirable to use the 1.8 V rail it is possible to connect the output stage to a 3.3 V rail. Care should be taken to not exceed the maximum junction temperature as the thermal dissipation increases with lower V_TT output voltages. For this reason it is not recommended to power PVIN off a rail higher than the nominal 3.3 V. The advantage of this configuration is that it has the ability to source and sink a higher maximum continuous current.

Figure 22. DDR-II Termination with Higher Voltage Rails

8.2.4 SSTL-2 Applications

For the majority of applications that implement the SSTL-2 termination scheme it is recommended to connect all the input rails to the 2.5 V rail. This provides an optimal trade-off between power dissipation and component count and selection. An example of this circuit can be seen in Figure 23.

Figure 23. Recommended SSTL-2 Implementation

If power dissipation or efficiency is a major concern then the LP2996A has the ability to operate on split power rails. The output stage (PVIN) can be operated on a lower rail such as 1.8 V and the analog circuitry (AVIN) can be connected to a higher rail such as 2.5 V, 3.3 V or 5 V. This allows the internal power dissipation to be lowered when sourcing current from V_TT. The disadvantage of this circuit is that the maximum continuous current is reduced because of the lower rail voltage, although it is adequate for all motherboard SSTL-2 applications. Increasing the output capacitance can also help if periods of large load transients will be encountered.

Figure 24. Lower Power Dissipation SSTL-2 Implementation

The third option for SSTL-2 applications in the situation that a 1.8 V rail is not available and it is not desirable to use 2.5 V, is to connect the LP2996A power rail to 3.3 V. In this situation AVIN will be limited to operation on the 3.3 V or 5 V rail as PVIN can never exceed AVIN. This configuration has the ability to provide the maximum continuous output current at the downside of higher thermal dissipation. Care should be taken to prevent the LP2996A from experiencing large current levels which cause the junction temperature to exceed the maximum. Because of this risk it is not recommended to supply the output stage with a voltage higher than a nominal 3.3 V rail.

Figure 25. SSTL-2 Implementation with Higher Voltage Rails

8.2.5 Level Shifting

If standards other than SSTL-2 are required, such as SSTL-3, it may be necessary to use a different scaling factor than 0.5 times V_DDQ for regulating the output voltage. Several options are available to scale the output to any voltage required. One method is to level shift the output by using feedback resistors from V_TT to the V_SENSE pin. This has been illustrated in Figure 26 and Figure 27. Figure 26 shows how to use two resistors to level shift V_TT above the internal reference voltage of VDDQ/2. To calculate the exact voltage at V_TT the following equation can be used.

Figure 26. Increasing VTT by Level Shifting

Conversely, the R2 resistor can be placed between V_SENSE and V_DDQ to shift the V_TT output lower than the internal reference voltage of VDDQ/2. The equations relating VTT and the resistors can be seen below:

Figure 27. Decreasing VTT by Level Shifting

8.2.6 HSTL Applications

The LP2996A can be easily adapted for HSTL applications by connecting V_DDQ to the 1.5 V rail. This will produce a V_TT and V_REF voltage of approximately 0.75 V for the termination resistors. AVIN and PVIN should be connected to a 2.5 V rail for optimal performance.

Figure 28. HSTL Application

8.2.7 QDR Applications

Quad data rate (QDR) applications utilize multiple channels for improved memory performance. However, this increase in bus lines has the effect of increasing the current levels required for termination. The recommended approach in terminating multiple channels is to use a dedicated LP2996A for each channel. This simplifies layout and reduces the internal power dissipation for each regulator. Separate V_REF signals can be used for each DIMM bank from the corresponding regulator with the chipset reference provided by a local resistor divider or one of the LP2996A signals. Because V_REF and V_TT are expected to track and the part to part variations are minor, there should be little difference between the reference signals of each LP2996A.