SNVS521K December   2007  – August 2014 LP2998 , LP2998-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
    1. 6.1 Pin Descriptions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings: LP2998
    3. 7.3 Handling Ratings: LP2998-Q1
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Thermal Information
    6. 7.6 Electrical Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Capacitor
      2. 9.1.2 Output Capacitor
      3. 9.1.3 Thermal Dissipation
    2. 9.2 Typical Application
      1. 9.2.1 DDR-III Applications
      2. 9.2.2 DDR-II Applications
      3. 9.2.3 SSTL-2 Applications
      4. 9.2.4 Level Shifting
        1. 9.2.4.1 Output Capacitor Selection
      5. 9.2.5 HSTL Applications
      6. 9.2.6 QDR Applications
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ

1 Features

  • AEC-Q100 Test Guidance with the following results (SO PowerPAD-8):
    • Device HBM ESD Classification Level H1C
    • Junction Temperature Range –40°C to 125°C
  • 1.35 V Minimum VDDQ
  • Source and Sink Current
  • Low Output Voltage Offset
  • No External Resistors Required
  • Linear Topology
  • Suspend to Ram (STR) Functionality
  • Low External Component Count
  • Thermal Shutdown

2 Applications

  • DDR1, DDR2, DDR3, and DDR3L Termination Voltage
  • Automotive Infotainment
  • FPGA
  • Industrial/Medical PC
  • SSTL-18, SSTL-2, and SSTL-3 Termination
  • HSTL Termination

3 Description

The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of DDR-SDRAM and DDR2 memory. The device also supports DDR3 and DDR3L VTT bus termination with VDDQ min of 1.35 V. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5 A continuous current and transient peaks up to 3 A in the application as required for DDR-SDRAM termination. The LP2998 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.

An additional feature found on the LP2998 is an active low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
LP2998 SO PowerPAD™ (8) 4.89 mm x 3.90 mm
LP2998 SOIC (8) 4.90 mm x 3.91 mm
LP2998-Q1 SO PowerPAD™ (8) 4.89 mm x 3.90 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

4 Simplified Schematic

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