8.3.1.1 Circuit Operation

The buck converter operates as follows: during the first portion of each switching cycle, the control block turns on the internal PFET switch. This allows current to flow from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a ramp with a slope of (V_IN – V_OUT)/L, by storing energy in a magnetic field.

During the second portion of each cycle, the controller turns the PFET switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor draws current from ground through the NFET to the output filter capacitor and load, which ramps the inductor current down with a slope of –V_OUT/L.

The output filter stores charge when the inductor current is high, and releases it when inductor current is low, smoothing the voltage across the load.

The output voltage is regulated by modulating the PFET switch on time to control the average current sent to the load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and synchronous rectifier at the SW pin to a low-pass filter formed by the inductor and output filter capacitor. The output voltage is equal to the average voltage at the SW pin.

8.3.1.2 PWM Operation

During pulse width modulation (PWM) operation the converter operates as a voltage mode controller with input voltage feed forward. This allows the converter to achieve good load and line regulation. The DC gain of the power stage is proportional to the input voltage. To eliminate this dependence, feed forward inversely proportional to the input voltage is introduced.

While in PWM mode, the output voltage is regulated by switching at a constant frequency and then modulating the energy per cycle to control power to the load. At the beginning of each clock cycle the PFET switch is turned on, and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The current limit comparator can also turn off the switch in case the current limit of the PFET is exceeded. Then the NFET switch is turned on and the inductor current ramps down. The next cycle is initiated by the clock turning off the NFET and turning on the PFET.

Figure 11. Typical PWM Operation

8.3.1.3 PFM Operation

At very light loads, the converter enters pulse frequency modulation (PFM) mode and operates with reduced switching frequency and supply current to maintain high efficiency.

The part automatically transitions into PFM mode when either of two conditions occurs for a duration of 32 or more clock cycles:

1. The inductor current becomes discontinuous.
2. The peak PMOS switch current drops below the I_MODE level (typically I_MODE < 30 mA + V_IN/42 Ω).

Figure 12. Typical PFM Operation

During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output FETs such that the output voltage ramps between < 0.6% and <1.7% above the nominal PWM output voltage. If the output voltage is below the high PFM comparator threshold, the PMOS power switch is turned on. It remains on until the output voltage reaches the high PFM threshold or the peak current exceeds the IPFM level set for PFM mode. The typical peak current in PFM mode is: I_PFM = 112 mA + V_IN/27 Ω. Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output voltage is below the high PFM comparator threshold (see Figure 13), the PMOS switch is again turned on and the cycle is repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output switches are turned off and the part enters an extremely low power mode. Quiescent supply current during this sleep mode is 21 µA (typical), which allows the part to achieve high efficiencies under extremely light load conditions. When the output drops below the low PFM threshold, the cycle repeats to restore the output voltage (average voltage in PFM mode) to < 1.15% above the nominal PWM output voltage. If the load current increases during PFM mode (see Figure 13) causing the output voltage to fall below the low2 PFM threshold, the device automatically transitions into fixed-frequency PWM mode. Typically when V_IN = 3.6 V the device transitions from PWM-to-PFM mode at 100-mA output current.

Figure 13. Operation in PFM Mode and Transfer to PWM Mode

8.3.1.4 Soft Start

The buck converter has a soft-start circuit that limits in-rush current during start-up. During start-up the switch current limit is increased in steps. Soft start is activated only if EN goes from logic low to logic high after V_IN reaches 2.7 V. Soft start is implemented by increasing switch current limit in steps of 213 mA, 425 mA, 850 mA and 1700 mA (typical switch current limit). The start-up time thereby depends on the output capacitor and load current demanded at start-up. Typical start-up time with a 10-µF output capacitor and 1000-mA load current is 390 µs and with a 1-mA load current, it is 295 µs.

8.3.1.5 Low Dropout (LDO) Operation

The LP3972 can operate at 100% duty cycle (no switching; PMOS switch completely on) for LDO support of the output voltage. In this way the output voltage is controlled down to the lowest possible input voltage. When the device operates near 100% duty cycle, output voltage ripple is approximately 25 mV. The minimum input voltage needed to support the output voltage is

8.3.1.6 Spread-Spectrum Feature

Periodic switching in the buck regulator is inherently a noisier function block compared to an LDO. It can be challenging in some critical applications to comply with stringent regulatory standards or simply to minimize interference to sensitive circuits in space limited portable systems. The regulator’s switching frequency and harmonics can cause noise in the signal spectrum. The magnitude of this noise is measured by its power spectral density. The power spectral density of the switching frequency, F_C, is one parameter that system designers want to be as low as practical to reduce interference to the environment and subsystems within their products. The LP3972 has a user selectable function on chip, wherein a noise reduction technique known as spread spectrum can be employed to ease customer’s design and production issues.

The principle behind spread spectrum is to modulate the switching frequency slightly and slowly, and spread the signal frequency over a broader bandwidth. Thus, its power spectral density becomes attenuated, and the associated interference electro-magnetic energy is reduced. The clock used to modulate the LP3972 buck regulator can be used as a spread spectrum clock via 2 I²C control register (System Control Register 1 (SCR1) 8h’80) bits bk_ssen, and slomod. With this feature enabled, the intense energy of the clock frequency can be spread across a small band of frequencies in the neighborhood of the center frequency. This results in a reduction of the peak energy.

The LP3972 spread-spectrum clock uses a triangular modulation profile with equal rise and fall slopes. The modulation has the following characteristics:

• The center frequency: f_C = 2 MHz, and
• The modulating frequency, ƒ_M = 6.8 kHz or 12 kHz.
• Peak frequency deviation: Δ_ƒ = ±100 kHz (or ±5%)
• Modulation index β = Δ_f/f_M = 14.7 or 8.3

Figure 14. Switching Energy RBW = 300 Hz

8.5.1.1 LP3972 Controls

8.5.1.1.5 Wake-up Functionality (PWR_ON, NTEST_JIG, SPARE and EXT_WAKEUP)

Three input pins can be used to assert wake-up output for 10 ms for application processor notification to wake up. SPARE Input can be programmed through I²C-compatible interface to be active low or high (SPARE bit, Default is active low 1). A reason for a wake-up event can be read through I²C-compatible interface also. Additionally, wake-up inputs have 30 ms de-bounce filtering, and PWR_ON distinguishes between short and long (∼1 s) pulses (push-button input). The LP3972 also has an internal thermal shutdown early warning that generates a wake-up to the system also. This is generated usually at 125°C.

Figure 15. Wake-Up Functionality

Table 5. Wake-Up Functions

WAKE-UP REGISTER BITS	REASON FOR WAKE-UP
WUP0	SPARE
WUP1	TEST_JIG
WUP2	PWR_ON short pulse
WUP3	PWR_ON long pulse
TSD_EW	TSD Early Warning

8.5.1.1.12 LP3972 Thermal Flags Functional Diagram, Data from Initial Silicon

Figure 16 shows extra features from the thermal shutdown circuit:

Figure 16. Thermal Shutdown Circuit Features

8.5.1.2 Initial Cold Start Power-On Sequence

1. The backup battery is connected to the PMU, power is applied to the backup battery pin, the LDO_RTC turns on and supplies a stable output voltage to the V_CC_BATT pin of the Applications processor (initiating the power-on reset event) with nRSTO asserted from the LP3972 to the processor.
2. nRSTO de-asserts after a minimum of 50 ms.
3. The applications processor waits for the de-assertion of nBATT_FLT to indicate system power (V_IN) is available.
4. After system power (V_IN) is applied, the LP3972 de-asserts nBATT_FLT. Note that BOTH nRSTO and nBATT_FLT need to be de-asserted before SYS_EN is enabled. The sequence of the two signals is independent of each other.
5. The Applications processor asserts SYS_EN, the LP3972 enables the system high-voltage power supplies. The applications processor starts its countdown timer set to 125 ms.
6. The LP3972 enables the high-voltage power supplies.
   • LDO1 power for V_CC_MVT (power for internal logic and I/O Blocks), BG (bandgap reference voltage), OSC13M (13-MHz oscillator voltage) and PLL enabled first, followed by others if delay is on.
7. Countdown timer expires; the applications processor asserts PWR_EN to enable the low-voltage power supplies. The processor starts the countdown timer set to 125 ms period.
8. The applications processor asserts PWR_EN (ext. pin or I²C), the LP3972 enables the low-voltage regulators.
9. Countdown timer expires; if enabled power domains are OK (I²C read) the power-up sequence continues by enabling the 13-MHz oscillator of the processor and PLLs.
10. The applications processor begins the execution of code.

See Power-On Timing Delays for more information.

* Note that BOTH nRSTO and nBATT_FLT need to be de-asserted before SYS_EN is enabled. The sequence of the two signals is independent of each other and can occur is either order.

Figure 17. Cold Start Power-On Efficiency

8.5.1.3 Hardware Reset Sequence

Hardware reset initiates when the nRSTI signal is asserted (low). Upon assertion of nRST the processor enters hardware reset state. The LP3972 holds the nRST low long enough (50 ms typica) to allow the processor time to initiate the reset state.

8.5.1.4 Reset Sequence

1. nRSTI is asserted.
2. nRSTO is asserted and de-asserts after a minimum of 50 ms.
3. The Applications processor waits for the de-assertion of nBATT_FLT to indicate system power (V_IN) is available.
4. After system power (V_IN) is turned on, the LP3972 de-asserts nBATT_FLT.
5. The applications processor asserts SYS_EN, the LP3972 enables the system high-voltage power supplies. The applications processor starts its countdown timer set to 125 ms.
6. The LP3972 enables the high-voltage power supplies.
7. Countdown timer expires; the applications processor asserts PWR_EN to enable the low-voltage power supplies. The processor starts the countdown timer set to 125 ms.
8. The applications processor asserts PWR_EN, the LP3972 enables the low-voltage regulators.
9. Countdown timer expires; if enabled power domains are OK (I²C read) the power-up sequence continues by enabling the 13-MHz oscillator of the processor and PLLs.
10. The applications processor begins the execution of code.

8.5.2.1 I²C Data Validity

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can only be changed when CLK is LOW.

Figure 18. Data Validity

8.5.2.2 I²C Start And Stop Conditions

START and STOP bits classify the beginning and the end of the I²C session. START condition is defined as SDA signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA transitioning from LOW to HIGH while SCL is HIGH. The I²C master always generates START and STOP bits. The I²C bus is considered to be busy after START condition and free after STOP condition. During data transmission, I²C master can generate repeated START conditions. First START and repeated START conditions are equivalent, function-wise.

Figure 19. Stop and Start Conditions

8.5.2.3 Transferring Data

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. The number of bytes that can be transmitted per transfer is unrestricted. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the 9th clock pulse, signifying an acknowledge. A receiver which has been addressed must generate an acknowledge after each byte has been received.

After the START condition, a chip address is sent by the I²C master. This address is seven bits long followed by an eighth bit which is a data direction bit (R/W). The LP3972 address is 34h. For the eighth bit, a 0 indicates a WRITE and a1 indicates a READ. The second byte selects the register to which the data will be written. The third byte contains data to write to the selected register.

8.5.2.4 I²C Chip Address - 7h'34

8.5.2.4.1 Write Cycle

Figure 20. Write Cycle

8.5.2.4.2 Read Cycle

When a READ function is to be accomplished, a WRITE function must precede the READ function as follows.

w = write (SDA = "0")

r = read (SDA = "1")

ack = acknowledge (SDA pulled down by either master or slave)

rs = repeated start

id = 34h (Chip Address)

Figure 21. Read Cycle

Figure 22. I²C DVM Timing For V_{CC_APPS} (Buck1)

8.5.2.5 Multi-Byte I²C Command Sequence

To correctly function with the Monahan’s Power Management I²C the I²C serial interface of the device supports random register multi-byte command sequencing: During a multi-byte write the Master sends the start command followed by the device address, which is sent only once, followed by the 8-bit register address, then 8 bits of data. The I²C slave must then accept the next random register address followed by 8 bits of data and continue this process until the master sends a valid stop condition.

A typical multi-byte random register transfer is outlined in the following:

Figure 23. Multi-Byte I²C Command

8.5.2.6 Incremental Register I²C Command Sequence

The LP3972 supports address increment (burst mode). When there is a defined register address n data bytes can be sent, and the register address is incremented after each data byte has been sent. Address incrimination may be required for non XScale applications. User can define whether multi-byte (default) to random address or address incrimination will be used.

Figure 24. Incremental Register I²C Command

8.6.1.1 System Control Status Register

Register is an 8-bit register which specifies the control bits for the PMIC clocks. This register works in conjunction with the SYNC pin where an external clock PLL buffer operating at 13 MHz is synchronized with the oscillators of the buck converters.

8.6.1.2 Output Voltage Enable Register 1

This register enables or disables the low voltage supplies LDO1 and Buck1. See details below.

8.6.1.3 Output Voltage Status Register

This 8-bit register is used to indicate the status of the low-voltage supplies. By polling each of the specify supplies is within its specified operating range.

8.6.1.4 Output Voltage Enable Register 2

This 8 bit output register enables and disables the output voltages on the LDOs 2,3,4 supplies.

8.6.1.5 Output Voltage Status Register 2

8.6.1.6 DVM Voltage Change Control Register 1

8.6.1.7 Buck1 (V_{CC_APPS}) Voltage 1

8.6.1.8 Buck1 (V_CC_APPS) Target Voltage 2 Register

8.6.1.9 Buck1 (V_CC_APPS) Voltage Ramp Control Register

8.6.1.10 V_CC_comm Target Voltage 1 Dummy Register (CDTV1)

8.6.1.11 V_CC_COMM Target Voltage 2 Dummy Register (CDTV2)

This is a variable voltage supply to the internal SRAM of the application processor.

8.6.1.12 LDO5 (V_CC_SRAM) Target Voltage 1 Register

8.6.1.13 LDO5 (V_CC_SRAM) Target Voltage 2 Register

8.6.1.14 LDO1 (V_{CC_MVT}) Target Voltage 1 Register (MDTV1)

8.6.1.15 LDO1 (V_{CC_MVT}) Target Voltage 2 Register

8.6.1.16 LDO2 Voltage Control Register (L12VCR)

8.6.1.17 LDO4 – LDO3 Voltage Control Register (L34VCR)

8.6.2.1 System Control Register 1 (SCR1)

8.6.2.2 System Control Register 2 (SCR2)

8.6.2.3 Output Enable 3 Register (OEN3) 8h’82

8.6.2.4 Output Enable 3 Register (OEN3) 8h’82 Definitions

8.6.2.5 Status Register 3 (OSR3) 8h’83

8.6.2.6 Status Register 3 (OSR3) Definitions 8h’83

8.6.2.7 Logic Output Enable Register (LOER) 8h’84

8.6.2.8 Logic Output Enable Register (LOER) Definitions 8h’84

8.6.2.9 V_CC_BUCK2 Target Voltage Register (B2TV) 8h’85

8.6.2.10 V_CC_BUCK2 Target Voltage Register (B2TV) 8h’85 Definitions

8.6.2.11 BUCK3 Target Voltage Register (B3TV) 8h’86

8.6.2.12 BUCK3 Target Voltage Register (B3TV) 8h’86 Definitions

8.6.2.13 V_CC_BUCK3:2 Voltage Ramp Control Register (B32RC)

8.6.2.14 Interrupt Status Register ISRA

This register specifies the status bits for the interrupts generated by the LP3972 device.

8.6.2.15 Backup Battery Charger Control Register (BCCR)

This register specifies the status of the main battery supply (NBUB bit).

8.6.2.16 Marvell PXA Internal 1 Revision Register (II1RR) 8h’8E

8.6.2.17 Marvell PXA Internal 1 Revision Register (II1RR) (Ii1rr) 8h’8E Definitions

8.6.2.18 Marvell PXA Internal 2 Revision Register (II1RR) 8h’8F

8.6.2.19 Marvell PXA Internal 2 Revision Register (II1RR) 8h’8F Definitions

8.6.2.20 Register Programming Examples

8.6.2.20.1 Example 1: Start-of-Day (SOD) Sequence

PMIC Register Address	PMIC Register Name	Register Data	Description
8h’23	ADTVI	00011011	Sets the SOD VCC_APPS voltage
8h’29	SDTV1	00011011	Sets the SOD VCC_SRAM voltage
8h’10	OVER1	00000111	Enables VCC_SRAM and VCC_APPS to their programmed values.

SODl multi-byte random register transfer is shown in Figure 25:

Figure 25. SOD Multi-Byte Random Register Transfer

Device Address

Register A Address, Ach, Register A Data, Ach Register M Address, Ach, Register M Data, Ach Register X Address, Ach, Register X Data, Ach Register Z Address, Ach, Register Z Data, Ach, Stop

8.6.2.20.3 I²C Data Exchange Between Master and Slave Device

Figure 26. Master and Slave Data Exchange