SNOSCR5D March   2013  – December 2016 LP55231

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Charge Pump Electrical Characteristics
    7. 6.7  LED Driver Electrical Characteristics
    8. 6.8  LED Test Electrical Characteristics
    9. 6.9  Logic Interface Characteristics
    10. 6.10 Recommended External Clock Source Conditions
    11. 6.11 Serial Bus Timing Parameters (SDA, SCL)
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Programming
      2. 7.3.2 LED Error Detection
      3. 7.3.3 Energy Efficiency
      4. 7.3.4 Temperature Compensation
      5. 7.3.5 Charge Pump Operational Description
        1. 7.3.5.1 Overview
        2. 7.3.5.2 Output Resistance
        3. 7.3.5.3 Controlling The Charge Pump
        4. 7.3.5.4 LED Forward Voltage Monitoring
        5. 7.3.5.5 Gain Change Hysteresis
      6. 7.3.6 LED Driver Operational Description
        1. 7.3.6.1 Overview
        2. 7.3.6.2 Powering LEDs
        3. 7.3.6.3 Controlling The High-Side LED Drivers
      7. 7.3.7 Automatic Power-Save Mode
      8. 7.3.8 PWM Power-Save Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes Of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Control Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 Start And Stop Conditions
        3. 7.5.1.3 Transferring Data
      2. 7.5.2 I2C-Compatible Chip Address
        1. 7.5.2.1 Control Register Write Cycle
        2. 7.5.2.2 Control Register Read Cycle
        3. 7.5.2.3 Auto-Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1 Register Set
      2. 7.6.2 Control Register Details
      3. 7.6.3 Instruction Set
      4. 7.6.4 LED Driver Instructions
        1. 7.6.4.1 Ramp
        2. 7.6.4.2 Ramp Instruction Application Example
        3. 7.6.4.3 Set_PWM
        4. 7.6.4.4 Wait
      5. 7.6.5 LED Mapping Instructions
        1. 7.6.5.1  MUX_LD_START; MUX_LD_END
        2. 7.6.5.2  MUX_MAP_START
        3. 7.6.5.3  MUX_SEL
        4. 7.6.5.4  MUX_CLR
        5. 7.6.5.5  MUX_MAP_NEXT
        6. 7.6.5.6  MUX_LD_NEXT
        7. 7.6.5.7  MUX_MAP_PREV
        8. 7.6.5.8  MUX_LD_PREV
        9. 7.6.5.9  MUX_MAP_ADDR
        10. 7.6.5.10 MUX_LD_ADDR
      6. 7.6.6 Branch Instructions
        1. 7.6.6.1 BRANCH
        2. 7.6.6.2 INT
        3. 7.6.6.3 RST
        4. 7.6.6.4 END
        5. 7.6.6.5 TRIGGER
      7. 7.6.7 Arithmetic Instructions
        1. 7.6.7.1 LD
        2. 7.6.7.2 ADD
        3. 7.6.7.3 SUB
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Using Two LP55231 in the Same Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Driving Haptic Feedback with LP55231
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Trademarks
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
Voltage Voltage on power pin VDD −0.3 6 V
Voltage on D1 to D9, C1−, C1+,
C2−, C2+, VOUT		 −0.3 V to VDD + 0.3 V with 6 V maximum V
Power Continuous power dissipation(3) Internally limited
Temperature Junction temperature, TJ-MAX 125 °C
Maximum lead temperature (soldering) See (4)
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage are with respect to the potential at the GND pin.
(3) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150°C (typical) and disengages at TJ = 130°C (typical).
(4) For detailed soldering specifications and information, refer to AN-1187 Leadless Leadframe Package (LLP).

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
Machine model: all pins ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)(1)
MIN NOM MAX UNIT
VDD Input voltage 2.7 5.5 V
Voltage on logic pins (input or output pins) 0 VDD V
IOUT Recommended charge pump load current 0 100 mA
TJ Junction temperature −30 125 °C
TA Ambient temperature(2) −30 85 °C
(1) All voltage are with respect to the potential at the GND pin.
(2) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).

6.4 Thermal Information

THERMAL METRIC(1) LP55231 UNIT
RTW (WQFN)
24 PINS
RθJA Junction-to-ambient thermal resistance 33.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 27.3 °C/W
RθJB Junction-to-board thermal resistance 11.4 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 11.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.2 °C/W
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

6.5 Electrical Characteristics

Typical (TYP) values apply for TA = 25°C and minimum (MIN) and maximum (MAX) apply over the operating ambient temperature range (−30°C < TA < 85°C). Specifications apply to the LP55231 Functional Block Diagram with: VDD = 3.6 V,
VEN = 1.65 V, COUT = 1 µF, CIN = 1 µF, C1–2 = 0.47 µF, unless otherwise specified.(1)(2)(3)(4)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IVDD Standby supply current VEN = 0V, CHIP_EN=0 (bit), external 32-kHz clock running or not running 0.2 1 µA
CHIP_EN=0 (bit), external 32-kHz clock not running 1 1.7 µA
CHIP_EN=0 (bit), external 32-kHz clock running 1.4 2.3 µA
Normal mode supply current External 32-kHz clock running, charge pump and current source outputs disabled 0.6 0.75 mA
Charge pump in 1× mode, no load, current source outputs disabled 0.8 0.95 mA
Charge pump in 1.5× mode, no load, current source outputs disabled 1.8 mA
Power save mode supply current External 32-kHz clock running 10 15 µA
Internal oscillator running 0.6 0.75 mA
ƒOSC Internal oscillator frequency accuracy TA = 25°C −4% 4%
–7% 7%
(1) The Electrical Characteristics tables list specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Test Conditions and/or Notes. Typical specifications are estimations only and are not verified.
(2) All voltages are with respect to the potential at the GND pin.
(3) Min and Max limits are verified by design, test, or statistical analysis.
(4) Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

6.6 Charge Pump Electrical Characteristics

Typical (TYP) values apply for TA = 25°C and minimum (MIN) and maximum (MAX) apply over the operating ambient temperature range (−30°C < TA < 85°C). Specifications apply to the LP55231 Functional Block Diagram with: VDD = 3.6 V,
VEN = 1.65 V, COUT = 1 µF, CIN = 1 µF, C1–2 = 0.47 µF, unless otherwise specified.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ROUT Charge pump output resistance Gain = 1.5×
Gain = 1×		 3.5
1		 Ω
ƒSW Switching frequency 1.25 MHz
IGND Ground current Gain = 1.5×
Gain = 1×		 1.2
0.3		 mA
tON VOUT turnon time(2) VDD = 3.6 V, IOUT = 60 mA 100 µs
(1) Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
(2) Turnon time is measured from the moment the charge pump is activated until the VOUT crosses 90% of its target value.

6.7 LED Driver Electrical Characteristics

Typical (TYP) values apply for TA = 25°C and minimum (MIN) and maximum (MAX) apply over the operating ambient temperature range (−30°C < TA < 85°C). Specifications apply to the LP55231 Functional Block Diagram with: VDD = 3.6 V, VEN = 1.65 V, COUT = 1 µF, CIN = 1 µF, C1–2 = 0.47 µF, unless otherwise specified.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ILEAKAGE Leakage current (outputs D1 to D9) PWM = 0% 0.1 1 µA
IMAX Maximum source current Outputs D1 to D9 25.5 mA
IOUT Output current accuracy(2) Output current set to 17.5 mA −4% 4%
Output current set to 17.5 mA, TA = 25°C –5% 5%
IMATCH Matching(2) Output current set to 17.5 mA, TA = 25°C 1% 2.5%
ƒLED LED switching frequency 312 Hz
VSAT Saturation voltage(3) Output current set to 17.5 mA
TA = 25°C		 45 100 mV
(1) Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
(2) Output Current Accuracy is the difference between the actual value of the output current and programmed value of this current. Matching is the maximum difference from the average. For the constant current outputs on the part (D1 to D9), the following are determined: the maximum output current (MAX), the minimum output current (MIN), and the average output current of all outputs (AVG). Two matching numbers are calculated: (MAX-AVG)/AVG and (AVG-MIN)/AVG. The largest number of the two (worst case) is considered the matching figure. Note that some manufacturers have different definitions in use.
(3) Saturation voltage is defined as the voltage when the LED current has dropped 10% from the value measured at VOUT – 1 V.

6.8 LED Test Electrical Characteristics

Typical (TYP) values apply for TA = 25°C and minimum (MIN) and maximum (MAX) apply over the operating ambient temperature range (−30°C < TA < 85°C). Specifications apply to the LP55231 Functional Block Diagram with: VDD = 3.6 V,
VEN = 1.65 V, COUT = 1 µF, CIN = 1 µF, C1–2 = 0.47 µF, unless otherwise specified.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LSB Least significant bit 30 mV
EABS Total unadjusted error(2) VIN_TEST = 0 V to VDD, TA = 25°C < ±3 ±4 LSB
tCONV Conversion time 2.7 ms
VIN_TEST DC voltage range TA = 25°C 0 5 V
(1) Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
(2) Total unadjusted error includes offset, full-scale, and linearity errors.

6.9 Logic Interface Characteristics

Typical (TYP) values apply for TA = 25°C and minimum (MIN) and maximum (MAX) apply over the operating ambient temperature range (−30°C < TA < 85°C). Specifications apply to the LP55231 Functional Block Diagram with: VDD = 3.6 V, VEN = 1.65 V, COUT = 1 µF, CIN = 1 µF, C1–2 = 0.47 µF, unless otherwise specified.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LOGIC INPUT EN
VIL Input low level 0.5 V
VIH Input high level 1.2 V
II Input current –1 1 µA
tDELAY Input delay(2) 2 µs
LOGIC INPUT SCL, SDA, TRIG, CLK, ASEL0, ASEL1
VIL Input low level 0.2 × VEN V
VIH Input high level 0.8 × VEN V
II Input current –1 1 µA
LOGIC OUTPUT SDA, TRIG, INT
VOL Output low level IOUT = 3 mA (pullup current) 0.3 0.5 V
IL Output leakage current VOUT = 2.8 V 1 µA
(1) Low-ESR surface-mount ceramic capacitors (MLCCs) used in setting electrical characteristics.
(2) The I2C host should allow at least 500 μs before sending data to the LP55231 after the rising edge of the enable line.

6.10 Recommended External Clock Source Conditions

See(1)(2)
MIN NOM MAX UNIT
LOGIC INPUT CLK
ƒCLK Clock frequency 32.7 kHz
tCLKH High time 6 µs
tCLKL Low time 6 µs
tr Clock rise time 10% to 90% 2 µs
tf Clock fall time 90% to 10% 2 µs
(1) Specification is verified by design and is not tested in production. VEN = 1.65 V to VDD.
(2) The ideal external clock signal for the LP55231 is a 0-V to VEN 25% to 75% duty-cycle square wave. At frequencies above 32.7 kHz, program execution is faster, and at frequencies below 32.7 kHz program execution is slower.

6.11 Serial Bus Timing Parameters (SDA, SCL)

See(1) and Figure 2
MIN MAX UNIT
ƒSCL Clock frequency 400 kHz
1 Hold time (repeated) START condition 0.6 µs
2 Clock low time 1.3 µs
3 Clock high time 600 ns
4 Setup time for a repeated START condition 600 ns
5 Data hold time 50 ns
6 Data setup time 100 ns
7 Rise time of SDA and SCL 20 + 0.1 Cb 300 ns
8 Fall time of SDA and SCL 15 + 0.1 Cb 300 ns
9 Setup time for STOP condition 600 ns
10 Bus free time between a STOP and a START condition 1.3 µs
Cb Capacitive load parameter for each bus line
Load of 1 pF corresponds to one nanosecond.		 10 200 ns
(1) Specification is verified by design and is not tested in production. VEN = 1.65 V to VDD.
LP55231 301986300.png Figure 1. External Clock Signal
LP55231 30198600.png Figure 2. Timing Parameters

6.12 Typical Characteristics

Unless otherwise specified: VDD = 3.6 V, CIN = COUT = 1 µF, C1 = C2 = 0.47 µF, TA = 25°C. CIN, COUT, C1, C2: Low-ESR surface-mount ceramic capacitors (MLCCs) used in setting electrical characteristics.
LP55231 301986301.png
Figure 3. Charge Pump 1.5× Efficiency vs Load Current
LP55231 301986305.png
6 × 1-mA Load (6 Nichia NSCW100 WLEDs On D1 To D6)
Figure 5. Gain Change Hysteresis Loop at Factory Settings
LP55231 301986306.png
17.5-mA Current
Figure 7. LED Current Matching Distribution
LP55231 30198677.gif
Charge Pump In 1× Mode
If the charge pump is OFF the supply current is even lower.
Figure 9. Power Save Mode Supply Current vs VDD
LP55231 30198649.gif
Figure 11. 100% PWM RGB LED Efficiency vs VDD
LP55231 301986303.png
Figure 4. Output Voltage of the Charge Pump (1.5×) as a Function of Load Current at Four Input Voltage Levels
LP55231 301986302.png
Load: 6 × Nichia NSCW100 WLEDs On D1 To D6 at 100% PWM
Figure 6. Effect of Adaptive Hysteresis on the Width of the Hysteresis Loop
LP55231 301986304.png
17.5-mA Current
Figure 8. LED Current Accuracy Distribution
LP55231 30198679.gif
51h To Addr 36h ILOAD = 60 mA VDD = 3.6 V
Figure 10. Serial Bus Write and Charge Pump Start-up Waveform
LP55231 30198650.gif
Figure 12. 100% PWM WLED Efficiency vs VDD