JAJSG45G May   2010  – September 2020 MSP430F5630 , MSP430F5631 , MSP430F5632 , MSP430F5633 , MSP430F5634 , MSP430F5635 , MSP430F5636 , MSP430F5637 , MSP430F5638

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 機能ブロック図
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Signal Descriptions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 8.6  Thermal Resistance Characteristics
    7. 8.7  Schmitt-Trigger Inputs – General-Purpose I/O
    8. 8.8  Inputs – Ports P1, P2, P3, and P4
    9. 8.9  Leakage Current – General-Purpose I/O
    10. 8.10 Outputs – General-Purpose I/O (Full Drive Strength)
    11. 8.11 Outputs – General-Purpose I/O (Reduced Drive Strength)
    12. 8.12 Output Frequency – Ports P1, P2, and P3
    13. 8.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    14. 8.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    15. 8.15 Crystal Oscillator, XT1, Low-Frequency Mode
    16. 8.16 Crystal Oscillator, XT2
    17. 8.17 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    18. 8.18 Internal Reference, Low-Frequency Oscillator (REFO)
    19. 8.19 DCO Frequency
    20. 8.20 PMM, Brownout Reset (BOR)
    21. 8.21 PMM, Core Voltage
    22. 8.22 PMM, SVS High Side
    23. 8.23 PMM, SVM High Side
    24. 8.24 PMM, SVS Low Side
    25. 8.25 PMM, SVM Low Side
    26. 8.26 Wake-up Times From Low-Power Modes and Reset
    27. 8.27 Timer_A, Timers TA0, TA1, and TA2
    28. 8.28 Timer_B, Timer TB0
    29. 8.29 Battery Backup
    30. 8.30 USCI (UART Mode)
    31. 8.31 USCI (SPI Master Mode)
    32. 8.32 USCI (SPI Slave Mode)
    33. 8.33 USCI (I2C Mode)
    34. 8.34 12-Bit ADC, Power Supply and Input Range Conditions
    35. 8.35 12-Bit ADC, Timing Parameters
    36. 8.36 12-Bit ADC, Linearity Parameters Using an External Reference Voltage
    37. 8.37 12-Bit ADC, Linearity Parameters Using AVCC as Reference Voltage
    38. 8.38 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
    39. 8.39 12-Bit ADC, Temperature Sensor and Built-In VMID
    40. 8.40 REF, External Reference
    41. 8.41 REF, Built-In Reference
    42. 8.42 12-Bit DAC, Supply Specifications
    43. 8.43 12-Bit DAC, Linearity Specifications
    44. 8.44 12-Bit DAC, Output Specifications
    45. 8.45 12-Bit DAC, Reference Input Specifications
    46. 8.46 12-Bit DAC, Dynamic Specifications
    47. 8.47 12-Bit DAC, Dynamic Specifications (Continued)
    48. 8.48 Comparator_B
    49. 8.49 Ports PU.0 and PU.1
    50. 8.50 USB Output Ports DP and DM
    51. 8.51 USB Input Ports DP and DM
    52. 8.52 USB-PWR (USB Power System)
    53. 8.53 USB-PLL (USB Phase-Locked Loop)
    54. 8.54 Flash Memory
    55. 8.55 JTAG and Spy-Bi-Wire Interface
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  CPU
    3. 9.3  Instruction Set
    4. 9.4  Operating Modes
    5. 9.5  Interrupt Vector Addresses
    6. 9.6  Memory
    7. 9.7  Bootloader (BSL)
      1. 9.7.1 USB BSL
      2. 9.7.2 UART BSL
    8. 9.8  JTAG Operation
      1. 9.8.1 JTAG Standard Interface
      2. 9.8.2 Spy-Bi-Wire Interface
    9. 9.9  Flash Memory
    10. 9.10 RAM
    11. 9.11 Backup RAM
    12. 9.12 Peripherals
      1. 9.12.1  Digital I/O
      2. 9.12.2  Port Mapping Controller
      3. 9.12.3  Oscillator and System Clock
      4. 9.12.4  Power-Management Module (PMM)
      5. 9.12.5  Hardware Multiplier (MPY) (Link to User's Guide)
      6. 9.12.6  Real-Time Clock (RTC_B)
      7. 9.12.7  Watchdog Timer (WDT_A)
      8. 9.12.8  System Module (SYS)
      9. 9.12.9  DMA Controller
      10. 9.12.10 Universal Serial Communication Interface (USCI)
      11. 9.12.11 Timer TA0
      12. 9.12.12 Timer TA1
      13. 9.12.13 Timer TA2
      14. 9.12.14 Timer TB0
      15. 9.12.15 Comparator_B
      16. 9.12.16 ADC12_A
      17. 9.12.17 DAC12_A
      18. 9.12.18 CRC16
      19. 9.12.19 Voltage Reference (REF) Module
      20. 9.12.20 USB Universal Serial Bus
      21. 9.12.21 Embedded Emulation Module (EEM)
      22. 9.12.22 Peripheral File Map
    13. 9.13 Input/Output Diagrams
      1. 9.13.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 9.13.2  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 9.13.3  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      4. 9.13.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 9.13.5  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      6. 9.13.6  Port P5 (P5.2 to P5.7) Input/Output With Schmitt Trigger
      7. 9.13.7  Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      8. 9.13.8  Port P7 (P7.2) Input/Output With Schmitt Trigger
      9. 9.13.9  Port P7 (P7.3) Input/Output With Schmitt Trigger
      10. 9.13.10 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
      11. 9.13.11 Port P8 (P8.0 to P8.7) Input/Output With Schmitt Trigger
      12. 9.13.12 Port P9 (P9.0 to P9.7) Input/Output With Schmitt Trigger
      13. 9.13.13 Port PU (PU.0/DP, PU.1/DM, PUR) USB Ports
      14. 9.13.14 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      15. 9.13.15 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    14. 9.14 Device Descriptors
  10. 10Device and Documentation Support
    1. 10.1  Getting Started and Next Steps
    2. 10.2  Device Nomenclature
    3. 10.3  Tools and Software
    4. 10.4  Documentation Support
    5. 10.5  Related Links
    6. 10.6  サポート・リソース
    7. 10.7  Trademarks
    8. 10.8  静電気放電に関する注意事項
    9. 10.9  Export Control Notice
    10. 10.10 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Revision History

Changes from revision F to revision G

Changes from September 18, 2018 to September 10, 2020

  • 文書全体にわたってセクション、表、図、相互参照の採番方法を更新Go
  • 文書全体にわたって nFBGA パッケージ (ZCA) の情報を追加Go
  • Removed package options that are no longer available in Table 6-1, Device Comparison (MSP430F5637 and MSP430F5631 in ZQW) Go
  • Updated the list of devices available in the 113-Pin ZQW package in the caption of Figure 7-4 Go
  • Changed the MAX value of the IERASE and IMERASE, IBANK parameters in Section 8.54, Flash Memory Go
  • Corrected the connection of the P7SEL.x signal in Figure 9-11, Port P7 (P7.4 to P7.7) Diagram Go

Changes from revision E to revision F

Changes from December 9, 2015 to September 17, 2018

  • Added Section 6.1, Related Products Go
  • Added typical conditions statements at the beginning of Section 8, Specifications Go
  • Changed the MIN value of the V(DVCC_BOR_hys) parameter from 60 mV to 50 mV in Section 8.20, PMM, Brownout Reset (BOR) Go
  • Updated notes (1) and (2) and added note (3) in Section 8.26, Wake-up Times From Low-Power Modes and Reset Go
  • Removed ADC12DIV from the formula for the TYP value in the second row of the tCONVERT parameter in Section 8.35, 12-Bit ADC, Timing Parameters, because ADC12CLK is after divisionGo
  • Removed the note that started "This impedance depends on..." from the "Reference input resistance" parameter in Section 8.45, 12-Bit DAC, Reference Input Specifications Go
  • Added second row for tEN_CMP with Test Conditions of "CBPWRMD = 10" and MAX value of 100 µs in Section 8.48, Comparator_B Go
  • Renamed FCTL4.MGR0 and MGR1 in the fMCLK,MGR parameter in Section 8.54, Flash Memory to be consistent with header files Go
  • Replaced former section Development Tools Support with Section 10.3, Tools and Software Go

Changes from revision D to revision E

Changes from August 6, 2013 to December 8, 2015

  • 全体を通してドキュメントのフォーマットと編成を変更、セクションの番号追加も含むGo
  • すべての機能ブロック図をSection 4「機能ブロック図」に移動 Go
  • Added USB column to Table 6-1, Family Members Go
  • Added Section 6, Device Comparison, and moved Table 6-1 to itGo
  • Added "Port U is supplied by the LDOO rail" to the PU.0 and PU.1 descriptions in Section 7.2, Signal Descriptions Go
  • Added Section 8.2, ESD Ratings Go
  • Added note to CVCORE Go
  • Added note to RPull Go
  • Changed TYP value of CL,eff with Test Conditions of "XTS = 0, XCAPx = 0" from 2 pF to 1 pFGo
  • In VBAT3 parameter description, changed from "VBAT3 ≠ VBAT/3" to "VBAT3 = VBAT/3"Go
  • Changed from fDAC12_0OUT to fDAC12_1OUT in the first row of the Test Conditions for the "Channel-to-channel crosstalk" parameterGo
  • Changed the value of DAC12_xDAT from 7F7h to F7Fh and changed the x-axis label from fToggle to 1/fToggle in Figure 8-22, Crosstalk Test Conditions Go
  • Added note to RPUR Go
  • Corrected the spelling of the MRG bits in the fMCLK,MRG parameter in Section 8.54, Flash Memory Go
  • Removed RTC_B from LPM4.5 wake-up optionsGo
  • Throughout document, changed all instances of "bootstrap loader" to "bootloader" Go
  • Added the paragraph that starts "Using the MSP430 RTC_B Module With Battery Backup Supply describes how..." Go
  • Corrected names of interrupt events PMMSWBOR (BOR) and PMMSWPOR (POR) in Table 9-11, System Module Interrupt Vector Registers Go
  • Corrected spelling of NMIIFG (added missing "I") in Table 9-11, System Module Interrupt Vector Registers Go
  • Corrected register acronyms (added "USB" prefix as required) in Table 9-50, USB Control Registers Go
  • Added P7SEL.2 and XT2BYPASS inputs with AND and OR gates in Figure 9-10, Port P7 (P7.3) Diagram Go
  • Changed P7SEL.3 column from X to 0 for "P7.3 (I/O)" rowsGo
  • Added Section 10 and moved Development Tools Support, Device and Development Tool Nomenclature, Trademarks, and Electrostatic Discharge Caution sections to itGo
  • Added Section 11, Mechanical, Packaging, and Orderable Information Go

The following table lists the changes to this data sheet from the original release through revision D.

REVISION COMMENTS
SLAS650D August 2013

Signal Descriptions, Added note regarding pullup resistor to RST/NMI/SBWTDIO pin.

Added Applications, Development Tools Support, and Device and Development Tool Nomenclature

Section 1, Changed the description of the number of I/Os in each port.

Table 1-3, Added PM5CTL0 register.

Section 1, Fixed typo in IDD Test Conditions (changed from DAC12IOG to DAC12OG).

Section 1, Corrected VIL and VIH limits.

Section 1, Changed IERASE and IMERASE, IBANK limits.
SLAS650C August 2012

Changed description of ACLK and PUR in Signal Descriptions.

Changed typos to Interrupt Flag names on Timer TA2 rows in Table 1-1.

Changed SYSRSTIV, System Reset offset 1Ch to Reserved in Table 1-1.

Corrected names of SVMLVLRIFG and SVMHVLRIFG bits in Table 1-1.

Corrected right-most column in Table 1-1.

Added note regarding evaluation of PUR in Section 1.

Changed notes on Section 1.

Changed tSENSOR(sample) MIN to 100 µs in Section 1.

Changed note (2) in Section 1.

Editorial changes throughout.
SLAS650B August 2011 Production Data release
SLAS650A July 2010 Updated Product Preview including electrical specifications
SLAS650 May 2010 Product Preview release

Changes from Revision () to Revision ()