JAJSG45G May 2010 – September 2020 MSP430F5630 , MSP430F5631 , MSP430F5632 , MSP430F5633 , MSP430F5634 , MSP430F5635 , MSP430F5636 , MSP430F5637 , MSP430F5638
PRODUCTION DATA
TI MSP 430™ ファミリの超低消費電力マイクロコントローラは複数のデバイスで構成され、それぞれが各種のアプリケーションを対象とする異なるペリフェラルを搭載しています。このアーキテクチャは 5 つの低消費電力モードを持ち、携帯用測定器用途でバッテリ駆動時間を延長するよう最適化されています。このデバイスには、強力な 16 ビット RISC CPU、16 ビット・レジスタ、および定数ジェネレータが搭載されており、コード効率が最大限に発揮されます。デジタル制御発振器 (DCO) により、低消費電力モードからアクティブ・モードへ 3µs (標準値) でウェークアップできます。
MSP430F563x は、高性能 12 ビット ADC、コンパレータ、2つの USCI、USB 2.0、ハードウェア乗算器、DMA、4 つの 16 ビット・タイマ、アラーム機能付き RTC モジュール、最大 74本の I/O ピンを搭載したマイクロコントローラです。
モジュールの完全な説明については、『MSP430F5xx および MSP430F6xx ファミリ・ユーザー・ガイド』を参照してください。
部品番号(1) | パッケージ | 本体サイズ(2) |
---|---|---|
MSP430F5638IPZ | LQFP (100) | 14mm × 14mm |
MSP430F5638IZCA | nFBGA (113) | 7mm × 7mm |
MSP430F5638IZQW(3) | MicroStar Junior™ BGA (113) | 7mm × 7mm |
Changes from revision F to revision G
Changes from September 18, 2018 to September 10, 2020
Changes from revision E to revision F
Changes from December 9, 2015 to September 17, 2018
Changes from revision D to revision E
Changes from August 6, 2013 to December 8, 2015
The following table lists the changes to this data sheet from the original release through revision D.
REVISION | COMMENTS |
---|---|
SLAS650D August 2013 |
Signal Descriptions, Added note regarding pullup resistor to RST/NMI/SBWTDIO pin. Added Applications, Development Tools Support, and Device and Development Tool Nomenclature Section 1, Changed the description of the number of I/Os in each port. Table 1-3, Added PM5CTL0 register. Section 1, Fixed typo in IDD Test Conditions (changed from DAC12IOG to DAC12OG). Section 1, Corrected VIL and VIH limits. Section 1, Changed IERASE and IMERASE, IBANK limits. |
SLAS650C August 2012 |
Changed description of ACLK and PUR in Signal Descriptions. Changed typos to Interrupt Flag names on Timer TA2 rows in Table 1-1. Changed SYSRSTIV, System Reset offset 1Ch to Reserved in Table 1-1. Corrected names of SVMLVLRIFG and SVMHVLRIFG bits in Table 1-1. Corrected right-most column in Table 1-1. Added note regarding evaluation of PUR in Section 1. Changed notes on Section 1. Changed tSENSOR(sample) MIN to 100 µs in Section 1. Changed note (2) in Section 1. Editorial changes throughout. |
SLAS650B August 2011 | Production Data release |
SLAS650A July 2010 | Updated Product Preview including electrical specifications |
SLAS650 May 2010 | Product Preview release |
Changes from Revision () to Revision ()
Table 6-1 summarizes the available family members.
DEVICE(1)(2) | FLASH (KB) |
SRAM (KB)(5) |
Timer_A(3) | Timer_B(4) | USCI_A: UART, IrDA, SPI |
USCI_B: SPI, I2C |
ADC12_A (Ch) |
DAC12_A (Ch) |
Comp_B (Ch) |
USB | I/O | PACKAGE |
---|---|---|---|---|---|---|---|---|---|---|---|---|
MSP430F5638 | 256 | 16 + 2 | 5, 3, 3 | 7 | 2 | 2 | 12 ext, 4 int | 2 | 12 | Yes | 74 | 100 PZ, 113 ZCA, 113 ZQW |
MSP430F5637 | 192 | 16 + 2 | 5, 3, 3 | 7 | 2 | 2 | 12 ext, 4 int | 2 | 12 | Yes | 74 | 100 PZ |
MSP430F5636 | 128 | 16 + 2 | 5, 3, 3 | 7 | 2 | 2 | 12 ext, 4 int | 2 | 12 | Yes | 74 | 100 PZ, 113 ZCA, 113 ZQW |
MSP430F5635 | 256 | 16 + 2 | 5, 3, 3 | 7 | 2 | 2 | 12 ext, 4 int | – | 12 | Yes | 74 | 100 PZ, 113 ZCA, 113 ZQW |
MSP430F5634 | 192 | 16 + 2 | 5, 3, 3 | 7 | 2 | 2 | 12 ext, 4 int | – | 12 | Yes | 74 | 100 PZ, 113 ZCA, 113 ZQW |
MSP430F5633 | 128 | 16 + 2 | 5, 3, 3 | 7 | 2 | 2 | 12 ext, 4 int | – | 12 | Yes | 74 | 100 PZ, 113 ZCA, 113 ZQW |
MSP430F5632 | 256 | 16 + 2 | 5, 3, 3 | 7 | 2 | 2 | – | – | 12 | Yes | 74 | 100 PZ, 113 ZCA, 113 ZQW |
MSP430F5631 | 192 | 16 + 2 | 5, 3, 3 | 7 | 2 | 2 | – | – | 12 | Yes | 74 | 100 PZ |
MSP430F5630 | 128 | 16 + 2 | 5, 3, 3 | 7 | 2 | 2 | – | – | 12 | Yes | 74 | 100 PZ, 113 ZCA, 113 ZQW |
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