JAJSG80 データシート

JAJSG80B May 2015 – September 2020 MSP430FG6425 , MSP430FG6426 , MSP430FG6625 , MSP430FG6626

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

PZ|100
- MTQF013A

サーマルパッド・メカニカル・データ

PZ|100
- QFND428

発注情報

8.8.3.1 Crystal Oscillator, XT1, Low-Frequency Mode

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
ΔI_DVCC,LF	Differential XT1 oscillator crystal current consumption from lowest drive setting, LF mode	f_OSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1	3 V		0.075		µA
		f_OSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 2			0.170
		f_OSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 3			0.290
f_XT1,LF0	XT1 oscillator crystal frequency, LF mode	XTS = 0, XT1BYPASS = 0			32768		Hz
f_XT1,LF,SW	XT1 oscillator logic-level square-wave input frequency, LF mode	XTS = 0, XT1BYPASS = 1⁽²⁾ ⁽³⁾		10	32.768	50	kHz
OA_LF	Oscillation allowance for LF crystals⁽⁴⁾	XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0, f_XT1,LF = 32768 Hz, C_L,eff = 6 pF			210		kΩ
OA_LF	Oscillation allowance for LF crystals⁽⁴⁾	XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1, f_XT1,LF = 32768 Hz, C_L,eff = 12 pF			300		kΩ
C_L,eff	Integrated effective load capacitance, LF mode⁽⁵⁾	XTS = 0, XCAPx = 0⁽⁶⁾			1		pF
		XTS = 0, XCAPx = 1			5.5
		XTS = 0, XCAPx = 2			8.5
		XTS = 0, XCAPx = 3			12.0
	Duty cycle, LF mode	XTS = 0, Measured at ACLK, f_XT1,LF = 32768 Hz		30%		70%
f_Fault,LF	Oscillator fault frequency, LF mode⁽⁷⁾	XTS = 0⁽⁸⁾		10		10000	Hz
t_START,LF	Start-up time, LF mode	f_OSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0, C_L,eff = 6 pF	3 V		1000		ms
t_START,LF	Start-up time, LF mode	f_OSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 3, C_L,eff = 12 pF	3 V		500		ms

(1) To improve EMI on the XT1 oscillator, observe the following guidelines.

Keep the trace between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.

(2) When XT1BYPASS is set, XT1 circuit is automatically powered down. Input signal is a digital square wave with parametrics defined in the Schmitt-trigger Inputs section of this data sheet.

(3) Maximum frequency of operation of the entire device cannot be exceeded.

(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following guidelines, but should be evaluated based on the actual crystal selected for the application:

For XT1DRIVEx = 0, C_L,eff ≤ 6 pF
For XT1DRIVEx = 1, 6 pF ≤ C_L,eff ≤ 9 pF
For XT1DRIVEx = 2, 6 pF ≤ C_L,eff ≤ 10 pF
For XT1DRIVEx = 3, C_L,ef_f ≥ 6 pF

(5) Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal.

(6) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.

(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specifications might set the flag.

(8) Measured with logic-level input frequency but also applies to operation with crystals.

Section 8.8.3.2 lists the characteristics of XT2.