JAJSJ79A August   2023  – December 2023 OPT4003-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Spectral Response
        1. 6.3.1.1 Channel 0: Human Eye Matching
        2. 6.3.1.2 Channel 1: Near Infrared
      2. 6.3.2 Automatic Full-Scale Range Setting
      3. 6.3.3 Error Correction Code (ECC) Features
        1. 6.3.3.1 Output Sample Counter
        2. 6.3.3.2 Output CRC
        3. 6.3.3.3 Threshold Detection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Modes of Operation
      2. 6.4.2 Interrupt Modes of Operation
      3. 6.4.3 Light Range Selection
      4. 6.4.4 Selecting Conversion Time
      5. 6.4.5 Light Measurement in Lux
      6. 6.4.6 Threshold Detection Calculations
      7. 6.4.7 Light Resolution
    5. 6.5 Programming
      1. 6.5.1 I2C Bus Overview
        1. 6.5.1.1 Serial Bus Address
        2. 6.5.1.2 Serial Interface
      2. 6.5.2 Writing and Reading
        1. 6.5.2.1 High-Speed I2C Mode
        2. 6.5.2.2 Burst Read Mode
        3. 6.5.2.3 General-Call Reset Command
        4. 6.5.2.4 SMBus Alert Response
  8. 7 Register Maps
    1. 7.1 Register Descriptions
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Electrical Interface
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Optical Interface
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Optomechanical Design
        3. 8.2.1.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Soldering and Handling Recommendations
      2. 8.5.2 Layout Example
  10. 9 デバイスおよびドキュメントのサポート
    1. 9.1 ドキュメントのサポート
      1. 9.1.1 関連資料
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 商標
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.4.2 Interrupt Modes of Operation

The device has an interrupt reporting system that allows the processor connected to the I2C bus to go to sleep, or otherwise ignore the device results, until a user-defined event occurs that requires possible action. Alternatively, this same mechanism can also be used with any system that can take advantage of a single digital signal that indicates whether the light is above or below levels of interest.

The INT pin has an open-drain output, which requires the use of a pullup resistor. This open-drain output allows multiple devices with open-drain INT pins to be connected to the same line, thus creating a logical NOR or AND function between the devices. The polarity of the INT pin can be controlled by the INT_POL register.

There are two major types of interrupt reporting mechanism modes: latched window comparison mode and transparent hysteresis comparison mode. The LATCH configuration register controls which of these two modes is used. Table 6-1 and Figure 6-3 summarize the function of these two modes. Additionally, the INT pin can either be used to indicate a fault in one of these modes (INT_CFG = 0) or to indicate a conversion completion (INT_CFG > 0). Table 6-2 details this functionality.

GUID-4C780270-8C60-4206-9836-FBF91431FCE1-low.pngFigure 6-3 Interrupt Pin Status (INT_CFG = 0 Setting) and Register Flag Behavior
Table 6-1 Interrupt Pin Status (INT_CFG = 0 Setting) and Register Flag Behavior
LATCH SETTING INT PIN STATE (WHEN INT_CFG=0) FLAG_H VALUE FLAG_L VALUE LATCHING BEHAVIOR
0: Transparent hysteresis mode The INT pin indicates if measurement is above (INT active) or below (INT inactive) the threshold. If measurement is between the high and low threshold values, then the previous INT value is maintained. This mode prevents the INT pin from repeated toggling when the measurement values are close to the threshold. 0: If measurement is below the low limit
1: If measurement is above the high limit
If measurement is between the high and low limits, the previous value is maintained.		 0: If measurement is above the high limit
1: If measurement is below the low limit
If measurement is between the high and low limits, the previous value is maintained.		 Not latching: Values are updated after each conversion
1: Latched window mode The INT pin becomes active if the measurement is outside the window (above the high threshold or below the low threshold). The INT pin does not reset and returns to the inactive state until the 0xC is register read. 1: If measurement is above the high limit 1: If measurement is below the low limit Latching: The INT pin, FLAG_H, and FLAG_L values do not reset until the 0x0C register is read.

The THRESHOLD_H, THRESHOLD_L, LATCH, and FAULT_COUNT registers control the interrupt behavior. As shown in Table 6-1, the LATCH field setting provides a choice between the latched window mode and transparent hysteresis mode. Interrupt reporting can be observed on the INT pin, the FLAG_H, and the FLAG_L registers.

Results from comparing the current sensor measurements with the THRESHOLD_H and THRESHOLD_L registers are referred to as fault events. See the Threshold Detection CalculationsLight Measurement in LuxThreshold Detection Calculations section for the calculations to set these registers. The FAULT_COUNT register dictates the number of continuous fault events required to trigger an interrupt event and subsequently change the state of the interrupt reporting mechanisms. For example, with a FAULT_COUNT value of 2 corresponding to four fault counts, the INT pin, FLAG_H, and FLAG_L states shown in Table 6-1 are not realized unless four consecutive measurements are taken that satisfy the fault condition.

The INT pin function listed in Table 6-1 is valid only when INT_CFG = 0. As described in Table 6-2, the INT pin function can be changed to indicate an end of conversion or FIFO full state. The FLAG_H and FLAG_L registers continue to behave as listed in Table 6-1, even while INT_CFG > 0. The polarity of the INT pin is controlled by the INT_POL register.

Table 6-2 INT_CFG Setting and Resulting INT Pin Behavior
INT_CFG SETTING INT PIN FUNCTION
0 As per Table 6-1
1 INT pin asserted with a 1-µs pulse duration after every conversion
2 INT pin asserted with a 1-µs pulse duration every two conversions to indicate both channel measurements are complete
3 INT pin asserted with a 1-µs pulse duration every four conversions to indicate the FIFO is full