JAJSFO1G September   2012  – June 2018 SN65DSI84

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     標準アプリケーション
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 EDS Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Clock Configurations and Multipliers
      2. 7.3.2 ULPS
      3. 7.3.3 LVDS Pattern Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset Implementation
      2. 7.4.2 Initialization Sequence
      3. 7.4.3 LVDS Output Formats
      4. 7.4.4 DSI Lane Merging
      5. 7.4.5 DSI Pixel Stream Packets
      6. 7.4.6 DSI Video Transmission Specifications
      7. 7.4.7 Operating Modes
    5. 7.5 Programming
      1. 7.5.1 Local I2C Interface Overview
    6. 7.6 Register Maps
      1. 7.6.1 Control and Status Registers Overview
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Video Stop and Restart Sequence
      2. 8.1.2 Reverse LVDS Pin Order Option
      3. 8.1.3 IRQ Usage
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Example Script
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 VCC Power Supply
    2. 9.2 VCORE Power Supply
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Package Specific
      2. 10.1.2 Differential Pairs
      3. 10.1.3 Ground
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VIL Low-level control signal input voltage 0.3 x VCC V
VIH High-level control signal input voltage 0.7 x VCC V
VOH High-level output voltage IOH = –4 mA 1.25 V
VOL Low-level output voltage IOL = 4 mA 0.4 V
ILKG Input failsafe leakage current VCC = 0; VCC(PIN) = 1.8 V ±30 μA
IIH High level input current Any input terminal ±30 μA
IIL Low level input current Any input terminal ±30 μA
IOZ High-impedance output current Any output terminal ±10 μA
IOS Short-circuit output current Any output driving GND short ±20 mA
ICC Device active current see (2) 106 150 mA
IULPS Device standby current All data and clock lanes are in ultra-low power state (ULPS) 7.7 10 mA
IRST Shutdown current EN = 0 0.04 0.06 mA
REN EN control input resistor 200 kΩ
MIPI DSI INTERFACE
VIH-LP LP receiver input high threshold See Figure 1 880 mV
VIL-LP LP receiver input low threshold See Figure 1 550 mV
|VID| HS differential input voltage 70 270 mV
|VIDT| HS differential input voltage threshold 50 mV
VIL-ULPS LP receiver input low threshold; ultra-low power state (ULPS) 300 mV
VCM-HS HS common mode voltage; steady-state 70 330 mV
ΔVCM-HS HS common mode peak-to-peak variation including symbol delta and interference 100 mV
VIH-HS HS single-ended input high voltage See Figure 1 460 mV
VIL-HS HS single-ended input low voltage See Figure 1 –40 mV
VTERM-EN HS termination enable; single-ended input voltage (both Dp AND Dn apply to enable) Termination is switched simultaneous for Dn and Dp 450 mV
RDIFF-HS HS mode differential input impedance 80 125 Ω
FLATLINK LVDS OUTPUT
|VOD| Steady-state differential output voltage for
A_Y x P/N and B_Y x P/N		 CSR 0x19.3:2=00 and, or CSR 0x19.1:0=00;
100 Ω near end termination		 180 245 313 mV
CSR 0x19.3:2=01 and/or CSR 0x19.1:0=01;
100 Ω near end termination		 215 293 372
CSR 0x19.3:2=10 and, or CSR 0x19.1:0=10;
100 Ω near end termination		 250 341 430
CSR 0x19.3:2=11 and/or CSR 0x19.1:0=11;
100 Ω near end termination		 290 389 488
CSR 0x19.3:2=00 and, or CSR 0x19.1:0=00;
200 Ω near end termination		 150 204 261
CSR 0x19.3:2=01 and, or CSR 0x19.1:0=01;
200 Ω near end termination		 200 271 346
CSR 0x19.3:2=10 and, or CSR 0x19.1:0=10;
200 Ω near end termination		 250 337 428
CSR 0x19.3:2=11 and, or CSR 0x19.1:0=11;
200 Ω near end termination		 300 402 511
Steady-state differential output voltage for
A_CLKP/N and B_CLKP/N		 CSR 0x19.3:2=00 and, or CSR 0x19.1:0=00
100 Ω near end termination		 140 191 244 mV
CSR 0x19.3:2=01 and, or CSR 0x19.1:0=01
100 Ω near end termination		 168 229 290
CSR 0x19.3:2=10 and, or CSR 0x19.1:0=10
100 Ω near end termination		 195 266 335
CSR 0x19.3:2=11 and, or CSR 0x19.1:0=11
100 Ω near end termination		 226 303 381
CSR 0x19.3:2=00 and, or CSR 0x19.1:0=00
200 Ω near end termination		 117 159 204
CSR 0x19.3:2=01 and, or CSR 0x19.1:0=01
200 Ω near end termination		 156 211 270
CSR 0x19.3:2=10 and, or CSR 0x19.1:0=10
200 Ω near end termination		 195 263 334
CSR 0x19.3:2=11 and, or CSR 0x19.1:0=11
200 Ω near end termination		 234 314 399
Δ|VOD| Change in steady-state differential output voltage between opposite binary states RL = 100 Ω 35 mV
VOC(SS) Steady state common-mode output voltage(3) CSR 0x19.6 = 1 and CSR 0x1B.6 = 1; and, or CSR 0x19.4 = 1 and
CSR 0x1B.4 = 1; see Figure 2 		0.8 0.9 1 V
CSR 0x19.6 = 0 and, or CSR 0x19.4 = 0; see Figure 2 1.15 1.25 1.35
VOC(PP) Peak-to-peak common-mode output voltage see Figure 2 35 mV
RLVDS_DIS Pull-down resistance for disabled LVDS outputs 1 kΩ
(1) All typical values are at VCC = 1.8 V and TA = 25°C
(2) SN65DSI84: SINGLE Channel DSI to DUAL Channel LVDS, 1440 x 900
  1. number of LVDS lanes = 2 x (3 data lanes + 1 CLK lane)
  2. number of DSI lanes = 2 data lanes + 1 CLK lane
  3. LVDS CLK OUT = 53.25 M
  4. DSI CLK = 500 M
  5. RGB888, LVDS18bpp
Maximum values are at VCC = 1.95 V and TA = 85°C
(3) Tested at VCC = 1.8 V , TA = –40°C for MIN, TA = 25°C for TYP, TA = 85°C for MAX.