JAJSQ80 データシート

JAJSQ80C september 2013 – october 2020 SN65DSI86

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

ZXH|64
- MPBGAK9A

サーマルパッド・メカニカル・データ

発注情報

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP⁽¹⁾	MAX	UNIT
STANDARD IO (TEST1, TEST2, ADDR, SCL, SDA, IRQ, REFCLK, EN, GPIO[4:1])
V_IL	Low-level control signal input voltage				0.3 × V_CCIO	V
V_IH	High-level control signal input voltage		0.7 × V_CCIO			V
V_OH	High-level output voltage	I_OH = –2 mA	1.3			V
V_OL	Low-level output voltage	I_OL = 2 mA			0.4	V
I_IH	High-level input current	Any input terminal			±5	μA
I_IL	Low-level input current	Any input terminal			±5	μA
I_OZ	High-impedance output current	Any output terminal			±10	μA
I_OS	Short-circuit output current	Any output driving GND short			±2	mA
I_CCA	V_CCA device active current	V_CCA = 1.2 V ⁽²⁾		70	126	mA
I_CC	V_CC device active current	V_CCA = 1.2 V ⁽²⁾		43	52	mA
I_CCIO	V_CCIO and V_PLL device active current	V_CCIO = 1.8 V, V_PLL = 1.8 V ⁽²⁾		32	32	mA
I_{SUSPEND_CCA}	V_CCA device suspend current	All data and clock lanes are in ultra-low power state (ULPS) and SUSPEND = 1		9.8		mA
I_{SUSPEND_CC}	V_CC device suspend current	All data and clock lanes are in ultra-low power state (ULPS) and SUSPEND = 1		9		mA
I_{SUSPEND_CCIO}	V_CCIO and V_PLL device suspend current	All data and clock lanes are in ultra-low power state (ULPS) and SUSPEND = 1		1.16		mA
I_{EN_CCA}	V_CCA shutdown current	EN = 0		0.95		mA
I_{EN_CC}	V_CC shutdown current	EN = 0		2		mA
I_{EN_CCIO}	V_CCIO and V_PLL shutdown current	EN = 0		0.038		mA
R_EN	EN control input resistor			150		kΩ
ADDR, EN, SCL, SDA, DBP/N[3:0], DAP/N[3:1], DBCP/N, DACP/N
I_LEAK	Input failsafe leakage current	V_CC = 0; V_CCIO = 0 V. Input pulled up to V_CCIO max. DSI inputs pulled up to 1.3 V	–40		40	µA
MIPI DSI INTERFACE
V_IH-LP	LP receiver input high threshold	See Figure 7-5	880			mV
V_IL-LP	LP receiver input low threshold	See Figure 7-5			550	mV
V_OH-LP	LP transmitter high-level output voltage		1100		1300	mV
V_OL-LP	LP transmitter low-level output voltage		–50		50	mV
V_IHCD	LP Logic 1 contention threshold		450			mV
V_ILCD	LP Logic 0 contention threshold				200	mV
\|V_ID\|	HS differential input voltage		70		270	mV
\|V_IDT\|	HS differential input voltage threshold				50	mV
V_IL-ULPS	LP receiver input low threshold; ultra-low power state (ULPS)				300	mV
V_CM-HS	HS common mode voltage; steady-state		70		330	mV
ΔV_CM-HS	HS common mode peak-to-peak variation including symbol delta and interference				100	mV
V_IH-HS	HS single-ended input high voltage	See Figure 7-5			460	mV
V_IL-HS	HS single-ended input low voltage	See Figure 7-5	–40			mV
V_TERM-EN	HS termination enable; single-ended input voltage (both Dp AND Dn apply to enable)	Termination is switched simultaneous for Dn and Dp			450	mV
R_DIFF-HS	HS mode differential input impedance		80		125	Ω
DisplayPort MAIN LINK
V_{TX_DC_CM}	Output common mode voltage		0		2	V
V_{TX_AC_CM_HBR_RBR}	TX AC common mode voltage for HBR and RBR.				20	mVRMS
V_{TX_AC_CM_HBR2}	TX AC common mode voltage for HBR2				30	mVRMS
V_{TX_DIFFPP_LVL0}	Differential peak-to-peak output voltage level 0	Based on default state of V0_P0_VOD register	300	400	460	mV
V_{TX_DIFFPP_LVL1}	Differential peak-to-peak output voltage level 1	Based on default state of V1_P0_VOD register	450	600	690	mV
V_{TX_DIFFPP_LVL2}	Differential peak-to-peak output voltage level 2	Based on default state of V2_P0_VOD register	600	800	920	mV
V_{TX_DIFFPP_LVL3}	Differential peak-to-peak output voltage level 3	Based on default state of V3_P0_VOD register. Level 3 is not enabled by default	600	800	920	mV
V_{TX_PRE_RATIO_0}	Pre-emphasis level 0		0	0	0	dB
V_{TX_PRE_RATIO_1}	Pre-emphasis level 1		2.8	3.5	4.2	dB
V_{TX_PRE_RATIO_2}	Pre-emphasis level 2		4.8	6.0	7.2	dB
V_{TX_PRE_RATIO_3}	Pre-emphasis level 3	Level 3 is not enabled by default	4.8	6.0	7.2	dB
V_{TX_PRE_POST2_RATIO_0}	Post-cursor2 level 0		0	0	0	dB
V_{TX_PRE_POST2_RATIO_1}	Post-cursor2 level 1		–1.1	–0.9	–0.7	dB
V_{TX_PRE_POST2_RATIO_2}	Post-cursor2 level 2		–2.3	–1.9	–1.5	dB
V_{TX_PRE_POST2_RATIO_3}	Post-cursor2 level 3	Level 3 is not enabled by default	–3.7	–3.1	–2.5	dB
I_{TX_SHORT}	TX short circuit current limit				50	mA
R_{TX_DIFF}	Differential impedance		80	100	120	Ω
C_{AC_COUPLING}	AC coupling capacitor		75		200	nF
DisplayPort HPD
V_{HPD_PLUG}	Hot plug detection threshold	Measured at 51-kΩ series resistor.	2.2			V
V_{HPD_UNPLUG}	Hot unplug detection threshold	Measured at 51-kΩ series resistor.			0.8	V
RHPDPD	HPD internal pulldown resistor		51	60	69	kΩ
DisplayPort AUX INTERFACE
V_{AUX_DIFF_PP_TX}	Peak-to-peak differential voltage at transmit pins	V_{AUX_DIFF_PP} = 2 × \|V_AUXP – V_AUXN\|	0.18		1.38	V
V_{AUX_DIFF_PP_RX}	Peak-to-peak differential voltage at receive pins	V_{AUX_DIFF_PP} = 2 × \|V_AUXP – V_AUXN\|	0.18		1.36	V
R_{AUX_TERM}	AUX channel termination DC resistance			100		Ω
V_{AUX_DC_CM}	AUX channel DC common mode voltage		0		1.2	V
V_{AUX_TURN_CM}	AUX channel turnaround common-mode voltage				0.3	V
I_{AUX_SHORT}	AUX Channel short circuit current limit				90	mA
C_AUX	AUX AC-coupling capacitor		75		200	nF

(1) All typical values are at V_CC = 1.2 V, V_CCA = 1.2 V, V_CCIO = 1.8 V, and V_PLL = 1.8 V, and T_A = 25°C

(2) Maximum condition: WQXGA 60 fps Dual-Link 2xDP at HBR2, PLL enabled; typical condition: WUXGA 60 fps 1xDP at HBR2, PLL enabled