Suspend mode is intended to be used with the Section 8.4.5.9 feature of the eDP sink. The PSR feature saves system power but this power savings must not produce any noticeable display artifacts to the end user. The deassertion of EN produces the greatest DSIx6 power savings, but the reconfiguration of the DSIx6 may be too slow, and therefore produce a bad end-user experience. In this case, Suspend mode is the next best option for reducing DSIx6 power consumption while in an active PSR state. Suspend mode allows for quick exit from an active PSR state.

When GPIO1 is configured for suspended operation (GPIO1 pin is asserted), then the DSIx6 is placed in low-power mode. The suspend (GPIO1) pin is sampled by the rising edge of REFCLK. If the suspend pin is sampled asserted, then all CSR registers do not reset to the default values, and the DP PLL, DP interface, and DSI interfaces are powered off, as shown in Figure 7-3. REFCLK can be turned off when DSIx6 is in Suspend mode. Section 7.6 summarizes the timing requirements to take the DSIx6 into Suspend mode.

The DSIx6 supports assertion of IRQ for HPD events. When an IRQ_HPD event is detected and both IRQ_EN and IRQ_HPD_EN bits are set, then the DSIx6 will assert the IRQ.

In order to take the DSIx6 out of Suspend mode, the REFCLK must be running before and after the suspend (GPIO1) pin is deasserted. After the DP PLL is locked, the DSIx6 transitions the ML_TX_MODE from Main Link Off to either Normal or Semi-Auto Link depending on the state of PSR_TRAIN register. If the PSR_EXIT_VIDEO bit is set, then active video begins transmitting over the DisplayPort interface after the first vertical sync start (VSS) is detected on the DSI interface. If the PSR_EXIT_VIDEO bit is not set, software must enable the VSTREAM_ENABLE bit. Then active video begins transmitting over the DisplayPort interface after the first vertical sync start The Section 7.6 table summarizes the timing requirements to take the DSIx6 into SUSPEND mode. (VSS) is detected on the DSI interface.