JAJSPZ6F May   2002  – March 2023 SN65HVD05 , SN65HVD06 , SN65HVD07 , SN75HVD05 , SN75HVD06 , SN75HVD07

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Package Dissipation Ratings
    5. 5.5 Driver Electrical Characteristics
    6. 5.6 Driver Switching Characteristics
    7. 5.7 Receiver Electrical Characteristics
    8. 5.8 Receiver Switching Characteristics
    9. 5.9 Typical Characteristics
      1.      Parameter Measurement Information
  6. 6 Function Tables
    1. 6.1 Receiver Failsafe
  7. 7 Equivalent Input and Output Schematic Diagrams
  8. 8 Application and Implementation
    1.     Typical Application
  9. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 商標
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.1 Receiver Failsafe

The differential receiver is “failsafe” to invalid bus states caused by:

  • open bus conditions such as a disconnected connector,
  • shorted bus conditions such as cable damage shorting the twisted-pair together, or
  • idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the differential receiver outputs a failsafe logic High state, so that the output of the receiver is not indeterminate.

Receiver failsafe is accomplished by offsetting the receiver thresholds so that the “input indeterminate” range does not include zero volts differential. To comply with the RS-422 and RS-485 standards, the receiver output must output a High when the differential input VID is more positive than +200 mV, and must output a Low when the VID is more negative than -200 mV. The receiver parameters which determine the failsafe performance are VIT+ and VIT- and VHYS. As seen in the Receiver Electrical Characteristics table, differential signals more negative than -200 mV will always cause a Low receiver output. Similarly, differential signals more positive than +200 mV will always cause a High receiver output.

When the differential input signal is close to zero, it will still be above the VIT+ threshold, and the receiver output is High. Only when the differential input is more negative than VIT- will the receiver output transition to a Low state. So, the noise immunity of the receiver inputs during a bus fault condition includes the receiver hysteresis value VHYS (the separation between VIT+ and VIT- ) as well as the value of VIT+.