JAJSND7P February   2002  – February 2022 SN65HVD10 , SN65HVD11 , SN65HVD12 , SN75HVD10 , SN75HVD11 , SN75HVD12

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Driver Electrical Characteristics
    6. 7.6  Receiver Electrical Characteristics
    7. 7.7  Power Dissipation Characteristics
    8. 7.8  Driver Switching Characteristics
    9. 7.9  Receiver Switching Characteristics
    10. 7.10 Dissipation Ratings
    11. 7.11 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 Low-Power Standby Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Data Rate and Bus Length
        2. 10.2.1.2 Stub Length
        3. 10.2.1.3 Bus Loading
        4. 10.2.1.4 Receiver Fail-safe
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
      1. 12.3.1 Thermal Characteristics of IC Packages
  13. 13Device and Documentation Support
    1. 13.1 Device Support
    2. 13.2 Related Links
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 サポート・リソース
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.2.1.4 Receiver Fail-safe

The differential receivers of the SN65HVD1x family are fail-safe to invalid bus states caused by:

  • Open bus conditions, such as a disconnected connector
  • Shorted bus conditions, such as cable damage shorting the twisted-pair together
  • Idle bus conditions that occur when no driver on the bus is actively driving.

In any of these cases, the differential receiver will output a fail-safe logic High state so that the output of the receiver is not indeterminate.

Receiver fail-safe is accomplished by offsetting the receiver thresholds, such that the input indeterminate range does not include zero volts differential. To comply with the RS-422 and RS-485 standards, the receiver output must output a High when the differential input VID is more positive than +200 mV, and must output a Low when VID is more negative than –200 mV. The receiver parameters which determine the fail-safe performance are VIT(+) and VIT(–). As shown in Section 7.6, differential signals more negative than –200 mV will always cause a Low receiver output, and differential signals more positive than +200 mV will always cause a High receiver output.

When the differential input signal is close to zero, it is still above the maximum VIT(+) threshold of –10 mV, and the receiver output will be High.