JAJSND7P February   2002  – February 2022 SN65HVD10 , SN65HVD11 , SN65HVD12 , SN75HVD10 , SN75HVD11 , SN75HVD12

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Driver Electrical Characteristics
    6. 7.6  Receiver Electrical Characteristics
    7. 7.7  Power Dissipation Characteristics
    8. 7.8  Driver Switching Characteristics
    9. 7.9  Receiver Switching Characteristics
    10. 7.10 Dissipation Ratings
    11. 7.11 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 Low-Power Standby Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Data Rate and Bus Length
        2. 10.2.1.2 Stub Length
        3. 10.2.1.3 Bus Loading
        4. 10.2.1.4 Receiver Fail-safe
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
      1. 12.3.1 Thermal Characteristics of IC Packages
  13. 13Device and Documentation Support
    1. 13.1 Device Support
    2. 13.2 Related Links
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 サポート・リソース
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.4 Device Functional Modes

When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input D. A logic high at D causes A to turn high and B to turn low. In this case, the differential output voltage defined as VOD = VA – VB is positive. When D is low, the output states reverse, B turns high, A becomes low, and VOD is negative.

When DE is low, both outputs turn high-impedance. In this condition, the logic state at D is irrelevant. The DE pin has an internal pulldown resistor to ground; therefore, when left open, the driver is disabled (high-impedance) by default. The D pin has an internal pullup resistor to VCC; therefore, when left open while the driver is enabled, output A turns high and B turns low.

Table 9-1 Driver Functions(1)
INPUTENABLEOUTPUTSFUNCTION
DDEAB
HHHLActively drive bus High
LHLHActively drive bus Low
XLZZDriver disabled
XOPENZZDriver disabled by default
OPENHHLActively drive bus High by default
(1) H = high level; L = low level; Z = high impedance; X = irrelevant; ? = indeterminate

When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage defined as VID = VA – VB is positive and higher than the positive input threshold, VIT+, the receiver output, R, turns high. When VID is negative and lower than the negative input threshold, VIT–, the receiver output, R, turns low. If VID is between VIT+ and VIT–, the output is indeterminate.

When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID are irrelevant. Internal biasing of the receiver inputs causes the output to go fail-safe-high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted (short-circuit), or when the bus is not actively driven (idle bus).

Table 9-2 Receiver Functions(1)
DIFFERENTIAL INPUT
VID = VA – VB		ENABLE
RE		OUTPUT
R		FUNCTION
VID > VIT+LHReceive valid bus High
VIT– < VID < VIT+L?Indeterminate bus state
VID < VIT–LLReceive valid bus Low
XHZReceiver disabled
XOPENZReceiver disabled by default
Open-circuit busLHFail-safe high output
Short-circuit busLHFail-safe high output
(1) H = high level; L = low level; Z = high impedance; X = irrelevant; ? = indeterminate