JAJSH42D February   2016  – October 2021 TCAN1042-Q1 , TCAN1042G-Q1 , TCAN1042GV-Q1 , TCAN1042H-Q1 , TCAN1042HG-Q1 , TCAN1042HGV-Q1 , TCAN1042HV-Q1 , TCAN1042V-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configurations and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 ESD Ratings, Specifications
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Thermal Information
    6. 7.6 Power Rating
    7. 7.7 Electrical Characteristics
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 TXD Dominant Timeout (DTO)
      2. 9.3.2 Thermal Shutdown (TSD)
      3. 9.3.3 Undervoltage Lockout
      4. 9.3.4 Unpowered Device
      5. 9.3.5 Floating Terminals
      6. 9.3.6 CAN Bus Short Circuit Current Limiting
      7. 9.3.7 Digital Inputs and Outputs
        1. 9.3.7.1 Devices with VCC Only (Devices without the "V" Suffix):
        2. 9.3.7.2 Devices with VIO I/O Level Shifting (Devices with "V" Suffix):
    4. 9.4 Device Functional Modes
      1. 9.4.1 CAN Bus States
      2. 9.4.2 Normal Mode
      3. 9.4.3 Standby Mode
        1. 9.4.3.1 Remote Wake Request via Wake Up Pattern (WUP) in Standby Mode
      4. 9.4.4 Driver and Receiver Function Tables
  10. 10Application Information Disclaimer
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Bus Loading, Length and Number of Nodes
      2. 10.2.2 Detailed Design Procedures
        1. 10.2.2.1 CAN Termination
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|8
  • DRB|8
サーマルパッド・メカニカル・データ
発注情報

7.8 Switching Characteristics

Over recommended operating conditions with TA = -55°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
Device Switching Characteristics
tPROP(LOOP1) Total loop delay, driver input (TXD) to receiver output (RXD), recessive to dominant See Figure 8-4, STB = 0 V,
RL = 60 Ω,
CL = 100 pF, CL(RXD) = 15 pF		 100 160 ns
tPROP(LOOP2) Total loop delay, driver input (TXD) to receiver output (RXD), dominant to recessive 110 175
tMODE Mode change time, from Normal to Standby or from Standby to Normal See Figure 8-3 9 45 µs
tWK_FILTER Filter time for valid wake up pattern 0.5 1.8 µs
Driver Switching Characteristics
tpHR Propagation delay time, high TXD to driver recessive (dominant to recessive) See Figure 8-1, STB = 0 V,
RL = 60 Ω,
CL = 100 pF, RCM = open		 75 ns
tpLD Propagation delay time, low TXD to driver dominant (recessive to dominant) 55
tsk(p) Pulse skew (|tpHR - tpLD|) 20
tR Differential output signal rise time 45
tF Differential output signal fall time 45
tTXD_DTO Dominant timeout See Figure 8-6, STB = 0 V,
RL = 60 Ω, CL = open		 1.2 3.8 ms
Receiver Switching Characteristics
tpRH Propagation delay time, bus recessive input to high output (Dominant to Recessive) See Figure 8-2, STB = 0 V,
CL(RXD) = 15 pF		 65 ns
tpDL Propagation delay time, bus dominant input to low output (Recessive to Dominant) 50 ns
tR RXD Output signal rise time 10 ns
tF RXD Output signal fall time 10 ns
FD Timing Parameters
tBIT(BUS) Bit time on CAN bus output pins with tBIT(TXD) = 500 ns, all devices See Figure 8-5 , STB = 0 V,
RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF,
ΔtREC = tBIT(RXD) - tBIT(BUS)		 435 530 ns
Bit time on CAN bus output pins with tBIT(TXD) = 200 ns, G device variants only 155 210
tBIT(RXD) Bit time on RXD output pins with tBIT(TXD) = 500 ns, all devices 400 550
Bit time on RXD output pins with tBIT(TXD) = 200 ns, G device variants only 120 220
ΔtREC Receiver timing symmetry with tBIT(TXD) = 500 ns, all devices -65 40
Receiver timing symmetry with tBIT(TXD) = 200 ns, G device variants only -45 15
(1) All typical values are at 25°C and supply voltages of VCC = 5 V and VIO = 5 V (if applicable), RL = 60 Ω