JAJSE38G November   2017  – December 2024 TCAN1043-Q1 , TCAN1043G-Q1 , TCAN1043H-Q1 , TCAN1043HG-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings IEC Specification
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Dissipation Ratings
    7. 6.7 Electrical Characteristics
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Internal and External Indicator Flags (nFAULT and RXD)
      2. 8.3.2 Power-Up Flag (PWRON)
      3. 8.3.3 Wake-Up Request Flag (WAKERQ)
      4. 8.3.4 Wake-Up Source Recognition Flag (WAKESR)
      5. 8.3.5 Undervoltage Fault Flags
        1. 8.3.5.1 Undervoltage on VCC Fault
        2. 8.3.5.2 Undervoltage on VIO Fault
        3. 8.3.5.3 Undervoltage on VSUP Fault
      6. 8.3.6 CAN Bus Failure Fault Flag
      7. 8.3.7 Local Faults
        1. 8.3.7.1 TXD Dominant Timeout (TXD DTO)
        2. 8.3.7.2 TXD Shorted to RXD Fault
        3. 8.3.7.3 CAN Bus Dominant Fault
        4. 8.3.7.4 Thermal Shutdown (TSD)
        5. 8.3.7.5 RXD Recessive Fault
        6. 8.3.7.6 Undervoltage Lockout (UVLO)
        7. 8.3.7.7 Unpowered Device
        8. 8.3.7.8 Floating Terminals
        9. 8.3.7.9 CAN Bus Short Circuit Current Limiting
    4. 8.4 Device Functional Modes
      1. 8.4.1 CAN Bus States
      2. 8.4.2 Normal Mode
      3. 8.4.3 Silent Mode
      4. 8.4.4 Standby Mode
      5. 8.4.5 Go-to-Sleep Mode
      6. 8.4.6 Sleep Mode with Remote Wake and Local Wake Up Requests
        1. 8.4.6.1 Remote Wake Request via Wake Up Pattern (WUP)
        2. 8.4.6.2 Local Wake Up (LWU) via WAKE Input Terminal
      7. 8.4.7 Driver and Receiver Function Tables
      8. 8.4.8 Digital Inputs and Outputs
      9. 8.4.9 INH (Inhibit) Output
  10. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Bus Loading, Length and Number of Nodes
      2. 9.2.2 Detailed Design Procedures
        1. 9.2.2.1 CAN Termination
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 サポート・リソース
    3. 10.3 商標
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|14
  • DMT|14
サーマルパッド・メカニカル・データ
発注情報

9.1 Application Information

The TCAN1043xx-Q1 transceivers are typically used in applications with a host microprocessor or FPGA that includes the data link layer portion of the CAN protocol. These types of applications usually also include power management technology that allows for power to be gated to the application via an enable (EN) or inhibit (INH) pin. A single 5V regulator can be used to drive both VCC and VIO as shown in Figure 9-1, or independent 5V and 3.3V regulators can be used to drive VCC and VIO separately as shown in Figure 9-2. The bus termination is shown for illustrative purposes.