JAJSDS3C September 2017 – December 2018 THVD1510 , THVD1512 , THVD1550 , THVD1551 , THVD1552
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
For this device, the driver and receiver are fully enabled, thus the differential outputs Y and Z follow the logic states at data input D at all times. A logic high at D causes Y to turn high and Z to turn low. In this case, the differential output voltage defined as VOD = VY – VZ is positive. When D is low, the output states reverse: Z turns high, Y becomes low, and VOD is negative. The D pin has an internal pull-up resistor to VCC, thus, when left open while the driver is enabled, output Y turns high and Z turns low.
INPUT | OUTPUTS | FUNCTIONS | |
---|---|---|---|
D | Y | Z | |
H | H | L | Actively drive bus high |
L | L | H | Actively drive bus low |
OPEN | H | L | Actively drive bus high by default |
When the differential input voltage defined as VID = VA – VB is higher than the positive input threshold, VTH+, the receiver output, R, turns high. When VID is less than the negative input threshold, VTH–, the receiver output, R, turns low. If VID is between VTH+ and VTH– the output is indeterminate. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted to one another (short-circuit), or the bus is not actively driven (idle bus).
DIFFERENTIAL INPUT | OUTPUT | FUNCTION |
---|---|---|
VID = VA – VB | R | |
VTH+ < VID | H | Receive valid bus high |
VTH- < VID < VTH+ | ? | Indeterminate bus state |
VID < VTH- | L | Receive valid bus low |
Open-circuit bus | H | Fail-safe high output |
Short-circuit bus | H | Fail-safe high output |
Idle (terminated) bus | H | Fail-safe high output |