JAJSO83B
May 2024 – October 2024
THVD2410V-EP
,
THVD2450V-EP
,
THVD2452V-EP
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
ESD Ratings [IEC]
5.4
Recommended Operating Conditions
5.5
Thermal Information
5.6
Power Dissipation
5.7
Electrical Characteristics
5.8
Switching Characteristics - 250 kbps
5.9
Switching Characteristics - 1 Mbps
5.10
Switching Characteristics - 20 Mbps
5.11
Switching Characteristics - 50 Mbps
5.12
Typical Characteristics
6
Parameter Measurement Information
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagrams
7.3
Feature Description
7.3.1
±70-V Fault Protection
7.3.2
Integrated IEC ESD and EFT Protection
7.3.3
Driver Overvoltage and Overcurrent Protection
7.3.4
Enhanced Receiver Noise Immunity
7.3.5
Receiver Fail-Safe Operation
7.3.6
Low-Power Shutdown Mode
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.1.1
Data Rate and Bus Length
8.2.1.2
Stub Length
8.2.1.3
Bus Loading
8.2.1.4
Transient Protection
8.2.2
Detailed Design Procedure
8.2.3
Application Curves
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Device Support
9.1.1
サード・パーティ製品に関する免責事項
9.2
ドキュメントの更新通知を受け取る方法
9.3
サポート・リソース
9.4
Trademarks
9.5
静電気放電に関する注意事項
9.6
用語集
10
Revision History
11
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DRC|10
MPDS117L
サーマルパッド・メカニカル・データ
DRC|10
QFND013N
発注情報
jajso83b_oa
jajso83b_pm
7.2
Functional Block Diagrams
Figure 7-1
THVD2410V-EP and THVD2450V-EP Block Diagram
Figure 7-2
THVD2452V-EP Block Diagram