JAJSE50 November   2017 TLA2021 , TLA2022 , TLA2024

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      システム監視アプリケーションの例
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 I2C Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1 Multiplexer
      2. 9.3.2 Analog Inputs
      3. 9.3.3 Full-Scale Range (FSR) and LSB Size
      4. 9.3.4 Voltage Reference
      5. 9.3.5 Oscillator
      6. 9.3.6 Output Data Rate and Conversion Time
    4. 9.4 Device Functional Modes
      1. 9.4.1 Reset and Power-Up
      2. 9.4.2 Operating Modes
        1. 9.4.2.1 Single-Shot Conversion Mode
        2. 9.4.2.2 Continuous-Conversion Mode
    5. 9.5 Programming
      1. 9.5.1 I2C Interface
        1. 9.5.1.1 I2C Address Selection
        2. 9.5.1.2 I2C Interface Speed
        3. 9.5.1.3 Serial Clock (SCL) and Serial Data (SDA)
        4. 9.5.1.4 I2C Data Transfer Protocol
        5. 9.5.1.5 Timeout
        6. 9.5.1.6 I2C General-Call (Software Reset)
      2. 9.5.2 Reading and Writing Register Data
        1. 9.5.2.1 Reading Conversion Data or the Configuration Register
        2. 9.5.2.2 Writing the Configuration Register
      3. 9.5.3 Data Format
  10. 10Register Maps
    1. 10.1 Conversion Data Register (RP = 00h) [reset = 0000h]
      1. Table 6. Conversion Data Register Field Descriptions
    2. 10.2 Configuration Register (RP = 01h) [reset = 8583h]
      1. Table 7. Configuration Register Field Descriptions
  11. 11Application and Implementation
    1. 11.1 Application Information
      1. 11.1.1 Basic Interface Connections
      2. 11.1.2 Connecting Multiple Devices
      3. 11.1.3 Single-Ended Signal Measurements
      4. 11.1.4 Analog Input Filtering
      5. 11.1.5 Duty Cycling To Reduce Power Consumption
      6. 11.1.6 I2C Communication Sequence Example
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
      3. 11.2.3 Application Curve
  12. 12Power Supply Recommendations
    1. 12.1 Power-Supply Sequencing
    2. 12.2 Power-Supply Decoupling
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14デバイスおよびドキュメントのサポート
    1. 14.1 デバイス・サポート
      1. 14.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 14.2 関連リンク
    3. 14.3 ドキュメントの更新通知を受け取る方法
    4. 14.4 コミュニティ・リソース
    5. 14.5 商標
    6. 14.6 静電気放電に関する注意事項
    7. 14.7 Glossary
  15. 15メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.2 Configuration Register (RP = 01h) [reset = 8583h]

The 16-bit configuration register controls the operating mode, input selection, data rate, and full-scale range.

Figure 17. Configuration Register
15 14 13 12 11 10 9 8
OS MUX[2:0] PGA[2:0] MODE
R/W-1h R/W-0h R/W-2h R/W-1h
7 6 5 4 3 2 1 0
DR[2:0] RESERVED
R/W-4h R/W-03h

Table 7. Configuration Register Field Descriptions

Bit Field Type Reset Description
15 OS R/W 1h

Operational Status or Single-Shot Conversion Start

This bit determines the operational status of the device. OS can only be written when in a power-down state and has no effect when a conversion is ongoing.

When writing:

0 : No effect

1 : Start a single conversion (when in a power-down state)

When reading:

0 : The device is currently performing a conversion

1 : The device is not currently performing a conversion (default)
14:12 MUX[2:0] R/W 0h

Input Multiplexer Configuration (TLA2024 only)

These bits configure the input multiplexer.

These bits serve no function on the TLA2021 and TLA2022 and are always set to 000.

000 : AINP = AIN0 and AINN = AIN1 (default)

001 : AINP = AIN0 and AINN = AIN3

010 : AINP = AIN1 and AINN = AIN3

011 : AINP = AIN2 and AINN = AIN3

100 : AINP = AIN0 and AINN = GND

101 : AINP = AIN1 and AINN = GND

110 : AINP = AIN2 and AINN = GND

111 : AINP = AIN3 and AINN = GND
11:9 PGA[2:0] R/W 2h

Programmable Gain Amplifier Configuration (TLA2022 and TLA2024 Only)

These bits set the FSR of the programmable gain amplifier.

These bits serve no function on the TLA2021 and are always set to 010.

000 : FSR = ±6.144 V(1)

001 : FSR = ±4.096 V(1)

010 : FSR = ±2.048 V (default)

011 : FSR = ±1.024 V

100 : FSR = ±0.512 V

101 : FSR = ±0.256 V

110 : FSR = ±0.256 V

111 : FSR = ±0.256 V
8 MODE R/W 1h

Operating Mode

This bit controls the operating mode.

0 : Continuous-conversion mode

1 : Single-shot conversion mode or power-down state (default)
7:5 DR[2:0] R/W 4h

Data Rate

These bits control the data rate setting.

000 : DR = 128 SPS

001 : DR = 250 SPS

010 : DR = 490 SPS

011 : DR = 920 SPS

100 : DR = 1600 SPS (default)

101 : DR = 2400 SPS

110 : DR = 3300 SPS

111 : DR = 3300 SPS
4:0 Reserved R/W 03h Always write 03h
(1) This parameter expresses the full-scale range of the ADC scaling. Do not apply more than VDD + 0.3 V to this device.