JAJSK64A March   2021  – April 2022 TLIN2021A-Q1

PRODMIX  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specification
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 ESD Ratings - IEC Specification
    4. 7.4 Thermal Information
    5. 7.5 Recommended Operating Conditions
    6. 7.6 Power Supply Characteristics
    7. 7.7 Electrical Characteristics
    8. 7.8 AC Switching Characteristics
    9. 7.9 Typical Curves
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  LIN
        1. 9.3.1.1 LIN Transmitter Characteristics
        2. 9.3.1.2 LIN Receiver Characteristics
          1. 9.3.1.2.1 Termination
      2. 9.3.2  TXD
      3. 9.3.3  RXD
      4. 9.3.4  VSUP
      5. 9.3.5  GND
      6. 9.3.6  EN
      7. 9.3.7  WAKE
      8. 9.3.8  INH
      9. 9.3.9  Local Faults
      10. 9.3.10 TXD Dominant Time-Out (DTO)
      11. 9.3.11 Bus Stuck Dominant System Fault: False Wake-Up Lockout
      12. 9.3.12 Thermal Shutdown
      13. 9.3.13 Under Voltage on VSUP
      14. 9.3.14 Unpowered Device
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Mode
      2. 9.4.2 Sleep Mode
      3. 9.4.3 Standby Mode
      4. 9.4.4 Wake-Up Events
        1. 9.4.4.1 Local Wake-Up (LWU) via WAKE Input Terminal
        2. 9.4.4.2 Wake-Up Request (RXD)
  10. 10Application Information Disclaimer
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedures
        1. 10.2.2.1 Normal Mode Application Note
        2. 10.2.2.2 TXD Dominant State Time-Out Application Note
        3. 10.2.2.3 Standby Mode Application Note
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.7 Electrical Characteristics

parameters valid across -40℃ ≤ TJ ≤ 150℃ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RXD Output Terminal
VOL Low-level voltage Based upon external pull-up to VCC(4) 0.6 V
IOL Low-level output current, open drain LIN = 0 V, RXD = 0.4 V 1.5 mA
ILKG Leakage current, high-level LIN = VSUP, RXD = VCC –5 5 µA
TXD Input Terminal
VIL Low-level input voltage 0.8 V
VIH High-level input voltage 2 V
ILKG Low-level input leakage current TXD = 0 V –5 5 µA
ITXD(WAKE) Local wake-up source recognition TXD Standby mode after a local wake-up event
VLIN = VSUP, WAKE = 0 V or VSUP, TXD = 1 V		 1.3 8 mA
RTXD Internal pull-down resistor value 125 350 800 kΩ
EN Input Terminal
VIL Low-level input voltage –0.3 0.8 V
VIH High-level input voltage 2 5.25 V
VHYS Hysteresis voltage By design and characterization 30 500 mV
IIL Low-level input current EN = 0 V –5 5 µA
REN Internal pull-down resistor 125 350 800 kΩ
LIN Terminal (Referenced to VSUP)
VOH LIN recessive high-level output voltage(3) TXD = VCC, IO = 0 mA
7 V ≤ VSUP ≤ 45 V		 0.85 VSUP
VOH LIN recessive high-level output voltage(1)(2) TXD = VCC, IO = 0 mA
7 V ≤ VSUP ≤ 18 V		 0.8 VSUP
VOH LIN recessive high-level output voltage(3) TXD = VCC, IO = 0 mA
4.5 V ≤ VSUP ≤ 7 V		 3 V
VOL LIN dominant low-level output voltage(3) TXD = 0 V
7 V ≤ VSUP ≤ 45 V		 0.2 VSUP
VOL LIN dominant low-level output voltage(1)(2) TXD = 0 V
7 V ≤ VSUP ≤ 18 V		 0.2 VSUP
VOL LIN dominant low-level output voltage(3) TXD = 0 V
4.5 V ≤ VSUP ≤ 7 V		 1.2 V
VBUSdom Low-level input voltage(3) LIN dominant (including LIN dominant for wake up)
See Figure 8-3 
See Figure 8-4		 0.4 VSUP
VBUSrec High-level input voltage(3) LIN recessive
See Figure 8-3 
See Figure 8-4		 0.6 VSUP
VIH LIN recessive high-level input voltage(1)(2) 7 V ≤ VSUP ≤ 18 V 0.47 0.6 VSUP
VIL LIN dominant low-level input voltge(1)(2) 7 V ≤ VSUP ≤ 18 V 0.4 0.53 VSUP
VSUP_NON_OP VSUP where impact of recessive LIN bus < 5%(3) TXD & RXD open
4.5 V ≤ VLIN ≤ 60 V		 –0.3 60 V
VBUS_CNT Receiver center threshold(3) VBUS_CNT = (VBUSrec + VBUSdom)/2
See Figure 8-3 
See Figure 8-4		 0.475 0.5 0.525 VSUP
VHYS Hysteresis voltage (ISO 17987) VHYS = VBUSrec - VBUSdom
See Figure 8-3 
See Figure 8-4		 0.175 VSUP
VHYS Hysteresis voltage (SAE J2602)
 		 VHYS = VIH - VIL
See Figure 8-3 
See Figure 8-4		 0.07 0.175 VSUP
VSERIAL_DIODE Serial diode LIN termination pull-up path  ISERIAL_DIODE = 10 µA 0.4 0.7 1.0 V
IBUS(LIM) Limiting current TXD = 0 V, VLIN = 36 V, RMeas = 480 Ω
VSUP = 36 V, VBUSdom < 10.224 V
 		 75 120 300 mA
IBUS_PAS_dom Receiver leakage current, dominant Driver off/recessive, LIN = 0 V
VSUP = 24 V
See Figure 8-6		 –1 mA
IBUS_PAS_rec1 Receiver leakage current, recessive Driver off/recessive, LIN ≥ VSUP
4.5 V ≤ VSUP ≤ 45 V
See Figure 8-7		 20 µA
IBUS_PAS_rec2 Receiver leakage current, recessive Driver off/recessive, LIN = VSUP
See Figure 8-7		 –5 5 µA
IBUS_NO_GND Leakage current, loss of ground GNDDevice = VSUP = 24 V
RMeas = 1 kΩ
0 V < VLIN < 36 V
 		 –1.5 1.5 mA
Ileak gnd(dom) Leakage current, loss of ground(5) VSUP = 8 V, GND = open, VSUP = 18 V, GND = open
RCommander = 1 kΩ, CL = 1 nF
RResponder = 20 kΩ, CL = 1 nF
LIN = dominant
 		 –1 1 mA
Ileak gnd(rec) Leakage current, loss of ground(5) VSUP = 8 V, GND = open, VSUP = 18 V, GND = open
RCommander = 1 kΩ, CL = 1 nF
RResponder = 20 kΩ, CL = 1 nF
LIN = recessive
 		 –100 100 µA
IBUS_NO_BAT Leakage current, loss of supply VSUP = GND
0 V ≤ VLIN ≤ 36 V
 		 5 µA
IRSLEEP Pull-up current source to VSUP sleep mode VSUP = 27 V, LIN = GND –20 –1.5 µA
RPU Pull-up resistor to VSUP  Normal and standby modes 20 45 60 kΩ
CLIN Capacitance of the LIN pin VSUP = 14 V 25 pF
INH Output Terminal
ΔVH High level voltage drop INH with respect to VSUP IINH = - 0.5 mA 0.5 1 V
ILKG(INH) Leakage current sleep mode INH = 0 V –0.5 0.5 µA
WAKE Input Terminal
VIH High-level input voltage Standby and sleep mode VSUP – 1.8 V
VIL Low-level input voltage Standby and sleep mode VSUP – 3.85 V
IIH High-level input leakage current WAKE = VSUP - 1 V –25 –12.5 µA
IIL Low-level input leakage current WAKE = 1 V 15 25 µA
tWAKE WAKE hold time Wake up time from sleep mode 5 50 µs
Duty Cycle Characteristics
D112V Duty cycle 1(3)
ISO 17987 Param 27		 THREC(MAX) = 0.744 x VSUP,
THDOM(MAX) = 0.581 x VSUP,
VSUP = 7 V to 18 V, tBIT = 50 µs
D1 = tBUS_rec(min)/(2 x tBIT)
See Figure 8-8 and Figure 8-9		 0.396
D112V Duty cycle 1(3)(6) THREC(MAX) = 0.665 x VSUP,
THDOM(MAX) = 0.499 x VSUP
VSUP = 4.5 V to 7 V, tBIT = 50 µs
D1 = tBUS_rec(min)/(2 x tBIT)
See Figure 8-8 and Figure 8-9		 0.396
D112V Duty cycle 1(1)(2)(6)
 		 THREC(MAX) = 0.744 x VSUP,
THDOM(MAX) = 0.581 x VSUP,
VSUP = 7 V to 18 V, tBIT = 52 µs
D1 = tBUS_rec(min)/(2 x tBIT)
See Figure 8-8 and Figure 8-9		 0.396
D212V Duty cycle 2(3)
ISO 17987 Param 28		 THREC(MIN) = 0.422 x VSUP,
THDOM(MIN) = 0.284 x VSUP,
VSUP = 7 V to 18 V, tBIT = 50 µs
D2 = tBUS_rec(MAX)/(2 x tBIT)
See Figure 8-8 and Figure 8-9		 0.581
D212V Duty cycle 2(3)(6) THREC(MIN) = 0.496 x VSUP,
THDOM(MIN) = 0.361 x VSUP,
VSUP = 4.5 V to 7 V, tBIT = 50 µs
D2 = tBUS_rec(MAX)/(2 x tBIT)
See Figure 8-8 and Figure 8-9		 0.581
D212V Duty cycle 2(1)(2)(6)
 		 THREC(MIN) = 0.422 x VSUP,
THDOM(MIN) = 0.284 x VSUP,
VSUP = 7 V to 18 V, tBIT = 52 µs
D2 = tBUS_rec(MAX)/(2 x tBIT)
See Figure 8-8 and Figure 8-9		 0.581
D312V Duty cycle 3(3)
ISO 17987 Param 29		 THREC(MAX) = 0.778 x VSUP
THDOM(MAX) = 0.616 x VSUP
VSUP = 7 V to 18 V, tBIT = 96 µs
D3 = tBUS_rec(min)/(2 x tBIT)
See Figure 8-8 and Figure 8-9		 0.417
D312V Duty cycle 3(3)(6) THREC(MAX) = 0.665 x VSUP
THDOM(MAX) = 0.499 x VSUP
VSUP = 4.5 V to 7 V, tBIT = 96 µs
D3 = tBUS_rec(min)/(2 x tBIT)
See Figure 8-8 and Figure 8-9		 0.417
D312V Duty cycle 3(1)(2)(6)
 		 THREC(MAX) = 0.778 x VSUP
THDOM(MAX) = 0.616 x VSUP
VSUP = 7 V to 18 V, tBIT = 96 µs
D3 = tBUS_rec(min)/(2 x tBIT)
See Figure 8-8 and Figure 8-9		 0.417
D412V Duty cycle 4(3)
ISO 17987 Param 30		 THREC(MIN) = 0.389 x VSUP
THDOM(MIN) = 0.251 x VSUP
VSUP = 7 V to 18 V, tBIT = 96 µs
D4 = tBUS_rec(MAX)/(2 x tBIT)
See Figure 8-8 and Figure 8-9		 0.59
D412V Duty cycle 4(3)(6) THREC(MAX) = 0.496 x VSUP
THDOM(MAX) = 0.361 x VSUP
VSUP = 4.5 V to 7 V, tBIT = 96 µs
D4 = tBUS_rec(MAX)/(2 x tBIT)
See Figure 8-8 and Figure 8-9		 0.59
D412V Duty cycle 4(1)(2)(6) THREC(MIN) = 0.389 x VSUP
THDOM(MIN) = 0.251 x VSUP
VSUP = 7 V to 18 V, tBIT = 96 µs
D4 = tBUS_rec(MAX)/(2 x tBIT)
See Figure 8-8 and Figure 8-9		 0.59
D124V Duty cycle 1
ISO 17987 Param 72		 THREC(MAX) = 0.710 x VSUP,
THDOM(MAX) = 0.554 x VSUP,
VSUP = 15 V to 36 V, tBIT = 50 µs
D1 = tBUS_rec(min)/(2 x tBIT)
See Figure 8-8 and Figure 8-9		 0.330
D224V Duty cycle 2
ISO 17987 Param 73		 THREC(MIN) = 0.446 x VSUP,
THDOM(MIN) = 0.302 x VSUP,
VSUP = 15.6 V to 36 V, tBIT = 50 µs
D2 = tBUS_rec(MAX)/(2 x tBIT)
See Figure 8-8 and Figure 8-9		 0.642
D324V Duty cycle 3
ISO 17987 Param 74		 THREC(MAX) = 0.744 x VSUP
THDOM(MAX) = 0.581 x VSUP
VSUP = 7 V to 36 V, tBIT = 96 µs
D3 = tBUS_rec(min)/(2 x tBIT)
See Figure 8-8 and Figure 8-9		 0.386
D324V Duty cycle 3 (6) THREC(MAX) = 0.645 x VSUP
THDOM(MAX) = 0.581 x VSUP
VSUP = 4.5 V to 7 V, tBIT = 96 µs
D3 = tBUS_rec(min)/(2 x tBIT)
See Figure 8-8 and Figure 8-9		 0.386
D424V Duty cycle 2 (6)
ISO 17987 Param 75		 THREC(MIN) = 0.422 x VSUP,
THDOM(MIN) = 0.284 x VSUP,
VSUP = 4.5 V to 36 V, tBIT = 96 µs
D2 = tBUS_rec(MAX)/(2 x tBIT)
See Figure 8-8 and Figure 8-9		 0.591
D1LB Duty cycle 1 at low battery(1)(2)(6) THREC(MAX) = 0.665 x VSUP,
THDOM(MAX) = 0.499 x VSUP,
VSUP = 5.5 V to 7 V, tBIT = 52 µs		 0.396
D2LB Duty cycle 2 at low battery(1)(2)(6) THREC(MAX) = 0.496 x VSUP
THDOM(MAX) = 0.361 x VSUP
VSUP = 6.1 V to 7 V, tBIT = 52 µs		 0.581
D3LB Duty cycle 3 at low battery(1)(2)(6) THREC(MAX) = 0.665 x VSUP,
THDOM(MAX) = 0.499 x VSUP,
VSUP = 5.5 V to 7 V, tBIT = 96 µs		 0.396
D4LB Duty cycle 4 at low battery(1)(2)(6) THREC(MAX) = 0.496 x VSUP
THDOM(MAX) = 0.361 x VSUP
VSUP = 6.1 V to 7 V, tBIT = 96 µs		 0.581
Tr-d max_D1 Transmitter propagation delay timings for the duty cycle(1)(2)(6)
Recessive to dominant		 THREC(MAX) = 0.744 x VSUP,
THDOM(MAX) = 0.581 x VSUP
7 V ≤ VSUP ≤ 18 V, tBIT = 52 µs
tREC(MAX)_D1 - tDOM(MIN)_D1		 10.8 µs
Td-r max_D2 Transmitter propagation delay timings for the duty cycle(1)(2)(6)
Dominant to recessive		 THREC(MAX) = 0.422 x VSUP,
THDOM(MAX) = 0.284 x VSUP
7 V ≤ VSUP ≤ 18 V, tBIT = 52 µs
tDOM(MAX)_D2 - tREC(MIN)_D2		 8.4 µs
Tr-d max_D3 Transmitter propagation delay timings for the duty cycle(1)(2)(6)
Recessive to dominant		 THREC(MAX) = 0.778 x VSUP
THDOM(MAX) = 0.616 x VSUP
7 V ≤ VSUP ≤ 18 V, tBIT = 96 µs
tREC(MAX)_D3 - tDOM(MIN)_D3		 15.9 µs
Td-r max_D4 Transmitter propagation delay timings for the duty cycle(1)(2)(6)
Dominant to recessive		 THREC(MIN) = 0.389 x VSUP
THDOM(MIN) = 0.251 x VSUP
7 V ≤ VSUP ≤ 18 V, tBIT = 96 µs
tDOM(MAX)_D4 - tREC(MIN)_D4		 17.28 µs
Tr-d max_low Low battery transmitter propagation delay timings for the duty cycle(1)(2)(6)
Recessive to dominant		 THREC(MAX) = 0.665 x VSUP,
THDOM(MAX) = 0.499 x VSUP
5.5 V ≤ VSUP ≤ 7 V, tBIT = 52 µs
tREC(MAX)_low - tDOM(MIN)_low		 10.8 µs
Td-r max_low Low battery transmitter propagation delay timings for the duty cycle(1)(2)(6)
Dominant to recessive		 THREC(MAX) = 0.496 x VSUP
THDOM(MAX) = 0.361 x VSUP
6.1 V ≤ VSUP ≤ 7 V, tBIT = 52 µs
tDOM(MAX)_low - tREC(MIN)_low		 8.4 µs
(1) SAE 2602 commander node load conditions: 5.5 nF/4 kΩ and 899 pF/20 kΩ
(2) SAE 2602 responder node load conditions: 5.5 nF/875 Ω and 899 pF/900 Ω
(3) ISO 17987 bus load conditions (CLINBUS, RLINBUS) include 1 nF/1 kΩ; 6.8 nF/660 Ω; 10 nF/500 Ω.
(4) RXD uses open drain output structure therefore VOL level is based upon microcontroller supply voltage.
(5) Ileak gnd = (VBAT - VLIN)/RLoad
(6) Specified by design