JAJSP02C march   2011  – april 2023 TLV3011-Q1 , TLV3011B-Q1 , TLV3012-Q1 , TLV3012B-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings TLV3012-Q1 DCK Package Only
    2. 6.2  Absolute Maximum Ratings - TLV301x-Q1 DBV Package, TLV3011B-Q1 and TLV3012B-Q1
    3. 6.3  ESD Ratings
    4. 6.4  Thermal Information - TLV3012-Q1 DCK Package Only
    5. 6.5  Thermal Information- TLV301x-Q1 DBV Package, TLV3011B-Q1 and TLV3012B-Q1
    6. 6.6  Recommended Operating Conditions
    7. 6.7  Electrical Characteristics - TLV3012-Q1 DCK Package Only
    8. 6.8  Switching Characteristics - TLV3012-Q1 DCK Package Only
    9. 6.9  Electrical Characteristics- TLV301x-Q1 DBV Package, TLV3011B-Q1 and TLV3012B-Q1
    10. 6.10 Switching Characteristics- TLV301x-Q1 DBV Package, TLV3011B-Q1 and TLV3012B-Q1
  7. 7 Typical Characteristics - TLV3012-Q1 DCK Package Only
  8. 8 Typical Characteristics - TLV301x-Q1 DBV Package, TLV3011B-Q1 and TLV3012B-Q1
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 Open Drain Output (TLV3011-Q1 and TLV3011B-Q1)
      2. 9.4.2 Push-Pull Output (TLV3012-Q1 and TLV3012B-Q1)
      3. 9.4.3 Voltage Reference
      4. 9.4.4 TLV3011B-Q1 and TLV3012B-Q1 Fail-Safe inputs
      5. 9.4.5 TLV3011B-Q1 and TLV3012B-Q1 Power On Reset
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 External Hysteresis
      2. 10.1.2 TLV3011B-Q1 and TLV3012B-Q1 Hysteresis
    2. 10.2 Typical Application
      1. 10.2.1 Under-Voltage Detection
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
    3. 10.3 System Examples
      1. 10.3.1 Power-On Reset
      2. 10.3.2 Relaxation Oscillator
    4. 10.4 Power Supply Recommendations
    5. 10.5 Layout
      1. 10.5.1 Layout Guidelines
      2. 10.5.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.9 Electrical Characteristics- TLV301x-Q1 DBV Package, TLV3011B-Q1 and TLV3012B-Q1

For VS (TOTAL SUPPLY VOLTAGE) = (V+) – (V–) = 1.8V and 5.5V,  VCM = VS /2 at TA = 25°C (Unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VCM = (V–) –6 ±0.3 6 mV
VOS Input offset voltage VCM = (V–)
TA = –40°C to +125°C		 –9 9 mV
dVIO/dT Input offset voltage drift VCM = (V–)
TA = –40°C to +125°C		 ±12 µV/°C
PSRR power supply rejection ratio VCM = (V–)
VS = 1.8 V to 5.5 V
TA = –40°C to +125°C		 100 1000 µV/V
PSRR power supply rejection ratio (B-Versions) VCM = (V–)
VS = 1.65 V to 5.5 V
TA = –40°C to +125°C		 100 1000 µV/V
VHYS Input hysteresis voltage TA = –40°C to +125°C 2 6 8 mV
INPUT BIAS CURRENT
IB Input bias current VCM =  VS /2  –10(1) ±4.5 10(1) pA
IOS Input offset current VCM =  VS /2  –10(1) ±1 10(1) pA
INPUT COMMON MODE RANGE
VCM-Range Common-mode voltage range VS = 1.8 V to 5.5 V (V–) – 0.2 (V+) + 0.2 V
CMRR Common mode rejection ratio VCM = (V–) + 1.5V to (V+) + 0.2V
VS = 5.5 V		 60 74 dB
CMRR Common mode rejection ratio VCM = (V–) - 0.2V to (V+) + 0.2V
VS = 5.5 V		 54 62 dB
RCM Input Common Mode Resistance 1013 Ω
CIC Input Common Mode Capacitance 2 pF
INPUT IMPEDANCE
RDM Input Differential Mode Resistance 1013 Ω
CID Input Differential Mode  Capacitance 4 pF
OUTPUT
VOL Voltage swing from (V–) VS = 5 V
ISINK = 5 mA
TA = –40°C to +125°C		 160 200 mV
VOH Voltage swing from (V+) (for Push-Pull only) VS = 5 V
ISOURCE = 5 mA
TA = –40°C to +125°C		 90 200 mV
VOLTAGE REFERENCE
VOUT Reference Voltage 1.223 1.242 1.260 V
Accuracy ±0.25% ±1.5%
dVOUT/dT Temperature Drift TA = –40°C to +125°C 40 100 ppm/℃
dVOUT/dILOAD Load Regulation, Sourcing 0 mA < ISOURCE ≤ 0.5 mA 0.36 1(1) mV/mA
Load Regulation, Sinking 0 mA < ISINK ≤ 0.5 mA 6.6
mV/mA
ILOAD Output Current 0.5 mA
dVOUT/dVS Line Regulation 1.8 V ≤ VS ≤ 5.5 V 10 100(1) µV/V
dVOUT/dVS Line Regulation (B-Versions) 1.65 V ≤ VS ≤ 5.5 V 10 100(1) µV/V
Vnoise Noise f = 0.1 Hz to 10 Hz 0.2 mVPP
POWER SUPPLY
IQ Quiescent current per comparator Output is logic high 2.8 5 µA
IQ Quiescent current per comparator Output is logic high
TA = –40°C to +125°C		 7 µA
IQ Quiescent current per comparator (B-Versions) Output is logic high 2.4 3.1 µA
IQ Quiescent current per comparator (B-Versions) Output is logic high
TA = –40°C to +125°C		 3.6 µA
(1) Ensured by characterization