JAJSDM5E September   2017  – November 2019 TLV7011 , TLV7012 , TLV7021 , TLV7022

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      X2SONパッケージと、SC70および米10セント硬貨との比較
      2.      伝搬遅延とオーバードライブとの関係
  4. 改訂履歴
  5. 概要 (続き)
  6. Pin Configuration and Functions
    1.     Pin Functions
    2.     Pin Functions: TLV7012/22
  7. Specifications
    1. 7.1  Absolute Maximum Ratings (Single)
    2. 7.2  Absolute Maximum Ratings (Dual)
    3. 7.3  ESD Ratings
    4. 7.4  Recommended Operating Conditions (Single)
    5. 7.5  Recommended Operating Conditions (Dual)
    6. 7.6  Thermal Information (Single)
    7. 7.7  Thermal Information (Dual)
    8. 7.8  Electrical Characteristics (Single)
    9. 7.9  Switching Characteristics (Single)
    10. 7.10 Electrical Characteristics (Dual)
    11. 7.11 Switching Characteristics (Dual)
    12. 7.12 Timing Diagrams
    13. 7.13 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Inputs
      2. 8.4.2 Internal Hysteresis
      3. 8.4.3 Output
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Inverting Comparator With Hysteresis for TLV701x
      2. 9.1.2 Noninverting Comparator With Hysteresis for TLV701x
    2. 9.2 Typical Applications
      1. 9.2.1 Window Comparator
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 IR Receiver Analog Front End
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
      3. 9.2.3 Square-Wave Oscillator
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
        1. 12.1.1.1 評価基板
    2. 12.2 関連リンク
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Detailed Design Procedure

The IR receiver AFE design is highly streamlined and optimized. R1 converts the IR light energy induced current into voltage and applies to the inverting input of the comparator. Because a reverse biased IR LED is used as the IR receiver, a higher I/V transimpedance gain is required to boost the amplitude of reduced current. A 10M resistor is used as R1 to support a 1-V, 100-nA transimpedance gain. This is made possible with the picoamps Input bias current IB (5pA typical). The RC network of R2 and C1 establishes a reference voltage Vref which tracks the mean amplitude of the IR signal. The RC constant of R2 and C1 (about 4.7 ms) is chosen for Vref to track the received IR current fluctuation but not the actual data bit stream. The noninverting input is connected to Vref and the output over the R3 and R4 resistor network which provides additional hysteresis for improved guard against spurious toggles.

To reduce the current drain from the coin cell battery, data transmission must be short and infrequent.