JAJSFH0G
february 2011 – june 2023
TLV707
,
TLV707P
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagrams
7.3
Feature Description
7.3.1
Internal Current Limit
7.3.2
Shutdown
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Input and Output Capacitor Requirements
8.2.2.2
Dropout Voltage
8.2.2.3
Transient Response
8.2.3
Application Curves
8.3
Best Design Practices
8.4
Power Supply Recommendations
8.5
Layout
8.5.1
Layout Guidelines
8.5.1.1
Board Layout Recommendations to Improve PSRR and Noise Performance
8.5.1.2
Package Mounting
8.5.1.3
Thermal Considerations
8.5.1.4
Power Dissipation
8.5.2
Layout Example
9
Device and Documentation Support
9.1
Device Support
9.1.1
Development Support
9.1.1.1
Evaluation Modules
9.1.1.2
Spice Models
9.1.2
Device Nomenclature
9.2
Documentation Support
9.2.1
Related Documentation
9.3
ドキュメントの更新通知を受け取る方法
9.4
サポート・リソース
9.5
Trademarks
9.6
静電気放電に関する注意事項
9.7
用語集
10
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DQN|4
MPSS021E
サーマルパッド・メカニカル・データ
DQN|4
QFND355C
発注情報
jajsfh0g_oa
jajsfh0g_pm
Data Sheet
TLV707、TLV707P
200mA、低 I
Q
、低ノイズ、低ドロップアウトの携帯型デバイス用レギュレータ