JAJSK01E
april 2011 – december 2020
TLV803
,
TLV853
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Device Comparison
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings #GUID-24157BEB-92B8-46F1-A3B7-B7A06F8BDB0C/SLVSA033153
7.2
ESD Ratings
7.3
Thermal Information
7.4
Recommended Operating Conditions
7.5
Electrical Characteristics
7.6
Switching Characteristics
7.7
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
VDD Transient Rejection
8.3.2
Reset During Power Up and Power Down
8.3.3
Bidirectional Reset Pins
8.4
Device Functional Modes
8.4.1
Normal Operation (VDD > Power-Up Reset Voltage)
8.4.2
Power On Reset (VDD < Power-Up Reset Voltage)
9
Application and Implementation
9.1
Application Information
9.1.1
Monitoring Multiple Supplies
9.1.2
Output Level Shifting
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Device Support
12.1.1
Development Support
12.1.1.1
Evaluation Modules
12.1.1.2
Spice Models
12.2
Documentation Support
12.2.1
Related Documentation
12.3
Related Links
12.4
サポート・リソース
12.5
Trademarks
12.6
静電気放電に関する注意事項
12.7
用語集
13
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DBZ|3
MPDS108G
サーマルパッド・メカニカル・データ
発注情報
jajsk01e_oa
jajsk01e_pm
7.6
Switching Characteristics
over operating temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
w
Pulse duration at V
DD
V
DD
= 1.08 V
IT–
to 0.92 V
IT–
10
µs
t
d
Delay time
V
DD
≥ V
IT–
+ 0.2 V; see
Timing Diagram
120
200
280
ms
Figure 7-1
Timing Diagram