JAJSK01E april   2011  – december 2020 TLV803 , TLV853

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1.     Pin Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings #GUID-24157BEB-92B8-46F1-A3B7-B7A06F8BDB0C/SLVSA033153
    2. 7.2 ESD Ratings
    3. 7.3 Thermal Information
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD Transient Rejection
      2. 8.3.2 Reset During Power Up and Power Down
      3. 8.3.3 Bidirectional Reset Pins
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > Power-Up Reset Voltage)
      2. 8.4.2 Power On Reset (VDD < Power-Up Reset Voltage)
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Monitoring Multiple Supplies
      2. 9.1.2 Output Level Shifting
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Evaluation Modules
        2. 12.1.1.2 Spice Models
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

over recommended operating junction temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
VOLLow-level output voltageVDD = 2 V to 6 V, IOL = 500 µA0.3V
VDD = 3.3 V, IOL = 2 mA0.4
VDD = 6 V, IOL = 4 mA0.4
Power-up reset voltage(1)IOL = 50 µA, VOL < 0.2 V1.1V
VIT–Negative-going input threshold voltage(2)TLV803ZTJ = – 40°C to +125°C2.202.252.30V
TLV803R2.582.642.70
TLV803S2.872.932.99
TLV8x3M4.284.384.48
VhysHysteresisTLV803ZTJ = 25°C, IOL = 50 µA30mV
TLV803R35
TLV803S40
TLV8x3M60
IDDSupply currentVDD = 2 V, output unconnected915µA
VDD = 6 V, output unconnected2030
IOHOutput leakage currentVDD = 6 V350nA
(1) The lowest supply voltage at which RESET becomes valid. tr,VDD ≤ 66.7 V/ms.
(2) To ensure best stability of the threshold voltage, place a bypass capacitor (0.1-µF ceramic) near the supply terminals.