JAJSD84K March   2017  – July 2024 TLV9061 , TLV9062 , TLV9064

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5.   Device Comparison Table
  6. 4 Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information: TLV9061
    5. 5.5  Thermal Information: TLV9061S
    6. 5.6  Thermal Information: TLV9062
    7. 5.7  Thermal Information: TLV9062S
    8. 5.8  Thermal Information: TLV9064
    9. 5.9  Thermal Information: TLV9064S
    10. 5.10 Electrical Characteristics
    11. 5.11 Typical Characteristics
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Rail-to-Rail Input
      2. 6.3.2 Rail-to-Rail Output
      3. 6.3.3 EMI Rejection
      4. 6.3.4 Overload Recovery
      5. 6.3.5 Shutdown Function
    4. 6.4 Device Functional Modes
  9. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Typical Low-Side Current Sense Application
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
      4. 7.2.4 Application Curve
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Input and ESD Protection
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  10. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  11. 9 Revision History
  12. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.10 Electrical Characteristics

For VS (Total Supply Voltage) = (V+) – (V–) = 1.8V to 5.5V at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
OFFSET VOLTAGE
VOSInput offset voltageVS = 5V±0.3±1.6mV
VS = 5V, TA = –40°C to 125°C±2
dVOS/dTDriftVS = 5V, TA = –40°C to 125°C±0.53µV/°C
PSRRPower-supply rejection ratioVS = 1.8V – 5.5V, VCM = (V–)±7±80µV/V
Channel separation, DCAt DC100dB
INPUT VOLTAGE RANGE
VCMCommon-mode voltage rangeVS = 1.8V to 5.5V(V–) – 0.1(V+) + 0.1V
CMRRCommon-mode rejection ratioVS = 5.5V, (V–) – 0.1V < VCM < (V+) – 1.4V,
TA = –40°C to 125°C		80103dB
VS = 5.5V, VCM = –0.1V to 5.6V,
TA = –40°C to 125°C		5787
VS = 1.8V, (V–) – 0.1V < VCM < (V+) – 1.4V,
TA = –40°C to 125°C		88
VS = 1.8V, VCM = –0.1V to 1.9V,
TA = –40°C to 125°C		81
INPUT BIAS CURRENT
IBInput bias current±0.5pA
IOSInput offset current±0.05pA
NOISE
EnInput voltage noise (peak-to-peak)VS = 5V, f = 0.1Hz to 10Hz4.77µVPP
enInput voltage noise densityVS = 5V, f = 10kHz10nV/√ Hz
VS = 5V, f = 1kHz16
inInput current noise densityf = 1kHz23fA/√ Hz
INPUT CAPACITANCE
CIDDifferential2pF
CICCommon-mode4pF
OPEN-LOOP GAIN
AOLOpen-loop voltage gainVS = 1.8V, (V–) + 0.04V < VO < (V+) – 0.04V,
RL = 10kΩ		100dB
VS = 5.5V, (V–) + 0.05V < VO < (V+) – 0.05V,
RL = 10kΩ		104130
VS = 1.8V, (V–) + 0.06V < VO < (V+) – 0.06V,
RL = 2kΩ		100
VS = 5.5V, (V–) + 0.15V < VO < (V+) – 0.15V,
RL = 2kΩ		130
FREQUENCY RESPONSE
GBPGain bandwidth productVS = 5V, G = +110MHz
φmPhase marginVS = 5V, G = +155°
SRSlew rateVS = 5V, G = +16.5V/µs
tSSettling timeTo 0.1%, VS = 5V, 2V step , G = +1, CL = 100pF0.5µs
To 0.01%, VS = 5V, 2V step,
G = +1, CL = 100pF		1
tOROverload recovery timeVS = 5V, VIN × gain > VS0.2µs
THD + NTotal harmonic distortion + noise(1)VS = 5.5V, VCM = 2.5V, VO = 1VRMS, G = +1,
f = 1kHz		0.0008%
OUTPUT
VOVoltage output swing from supply railsVS = 5.5V, RL = 10kΩ20mV
VS = 5.5V, RL = 2kΩ60
ISCShort-circuit currentVS = 5V±50mA
ZOOpen-loop output impedanceVS = 5V, f = 10MHz100Ω
POWER SUPPLY
IQQuiescent current per amplifierVS = 5.5V, IO = 0mA538750µA
VS = 5.5V, IO = 0mA, TA = –40°C to 125°C800
SHUTDOWN
IQSDQuiescent current per amplifierVS = 1.8V to 5.5V, all amplifiers disabled,
SHDN = Low		0.51.5µA
ZSHDNOutput impedance during shutdownVS = 1.8V to 5.5V, amplifier disabled10 || 8GΩ || pF
VSHDN_THR_HIHigh level voltage shutdown threshold (amplifier enabled)VS = 1.8V to 5.5V(V–) + 0.9V(V–) + 1.1VV
VSDHN_THR_LOLow level voltage shutdown threshold (amplifier disabled)VS = 1.8V to 5.5V(V–) + 0.2V(V–) + 0.7VV
tONAmplifier enable time (shutdown)(2)VS = 1.8V to 5.5V, full shutdown; G = 1,
VOUT = 0.9 × VS / 2, RL connected to V–		10µs
tOFFAmplifier disable time(2)VS = 1.8V to 5.5V, G = 1, VOUT = 0.1 × VS / 2,
RL connected to V–		0.6µs
SHDN pin input bias current (per pin)VS = 1.8V to 5.5V, V+ ≥ SHDN ≥ (V+) – 0.8V130pA
VS = 1.8V to 5.5V, V– ≤ SHDN ≤ V– + 0.8V40
(1) Third-order filter; bandwidth = 80kHz at –3dB.
(2) Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.