SLASE75D August   2015  – September 2017 TMDS181

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Electrical Characteristics
    6. 6.6  TMDS Differential Input Electrical Characteristics
    7. 6.7  TMDS Differential Output Electrical Characteristics
    8. 6.8  DDC, I2C, HPD, and ARC Electrical Characteristics
    9. 6.9  Power-Up and Operation Timing Requirements
    10. 6.10 TMDS Switching Characteristics
    11. 6.11 HPD Switching Characteristics
    12. 6.12 DDC and I2C Switching Characteristics
    13. 6.13 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Reset Implementation
      2. 8.3.2  Operation Timing
      3. 8.3.3  Swap and Polarity Working
      4. 8.3.4  TMDS Inputs
      5. 8.3.5  TMDS Inputs Debug Tools
      6. 8.3.6  Receiver Equalizer
      7. 8.3.7  Input Signal Detect Block
      8. 8.3.8  Audio Return Channel
      9. 8.3.9  Transmitter Impedance Control
      10. 8.3.10 TMDS Outputs
      11. 8.3.11 Pre-Emphasis/De-Emphasis
    4. 8.4 Device Functional Modes
      1. 8.4.1 Retimer Mode
      2. 8.4.2 Redriver Mode
      3. 8.4.3 DDC Training for HDMI2.0a Data Rate Monitor
      4. 8.4.4 DDC Functional Description
      5. 8.4.5 Mode Selection Functional Description
    5. 8.5 Register Maps
      1. 8.5.1 Local I2C Overview
      2. 8.5.2 Local I2C Control Bit Access TAG Convention
      3. 8.5.3 CSR Bit Field Definitions
        1. 8.5.3.1 ID Registers
        2. 8.5.3.2 MISC CONTROL Register
        3. 8.5.3.3 Equalization Control Register
        4. 8.5.3.4 RX PATTERN VERIFIER CONTROL/STATUS Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Source Side Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Sink Side Application
      3. 9.2.3 Application Chain Showing DDC Connections
        1. 9.2.3.1 Detailed Design Procedure
          1. 9.2.3.1.1 DDC Pullup Resistors
          2. 9.2.3.1.2 Compliance Testing
            1. 9.2.3.1.2.1 Pin Strapping Configuration for HDMI2.0a and HDMI1.4b
            2. 9.2.3.1.2.2 I2C Control for HDMI2.0a and HDMI1.4b
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Parameter Measurement Information

TMDS181 TMDS181I tim_TMDS_main_link_LASE75.gif Figure 6. TMDS Main Link Test Circuit
TMDS181 TMDS181I tim_io_LASE75.gif Figure 7. Input/Output Timing Measurements
TMDS181 TMDS181I tim_TMDS_output_LASE75.gif Figure 8. TMDS Output Skew Measurements
TMDS181 TMDS181I tim_HDMI_LASE75.gif Figure 9. HDMI/DVI TMDS Output Common Mode Measurement
TMDS181 TMDS181I tim_output_pre-emp_LASE75.gif Figure 10. Output Differential Waveform
TMDS181 TMDS181I PRE_SEL_L_lase75.gif Figure 11. Output De-Emphasis Waveform
TMDS181 TMDS181I HDMI_output_LASE75.gif
A. The FR4 trace between TTP1 and TTP2 is designed to emulate 1 to 8 inches of FR4, AC coupling capacitor, connector, and another 1 to 8 inches of FR4. Trace width = 4 mils. 100-Ω differential impedance.
B. All jitter is measured at a BER of 10-9
C. Residual jitter reflects the total jitter measured at TTP4 minus the jitter measured at TTP1
D. AVCC = 3.3 V
E. RT = 50 Ω,
F. The input signal from parallel Bert does not have any pre-emphasis. Refer to Recommended Operating Conditions.
Figure 12. HDMI Output Jitter Measurement
TMDS181 TMDS181I input_eyemask_LASE75.gif Figure 13. Input Eye Mask Post EQ – TTP2_EQ
TMDS181 TMDS181I output_eyemask_LASE75.gif
A. See Table 1.
Figure 14. Output Eye Mask at TTP4_EQ

Table 1. Output Eye Mask V and H Values

TMDS Data Rate (Gbps) H (Tbit) V (mV)
3.4 < DR < 3.712 0.6 335
3.712 < DR < 5.94 –0.0332Rbit2 +0.2312 Rbit + 0.1998 –19.66Rbit2 + 106.74Rbit + 209.58
5.94 ≤ DR ≤ 6.0 0.4 150
TMDS181 TMDS181I HPD_test_LASE75.gif Figure 15. HPD Test Circuit
TMDS181 TMDS181I tim_HPD_1_LASE75.gif Figure 16. HPD Timing Diagram 1
TMDS181 TMDS181I logic_disconnect_LASE75.gif Figure 17. HPD Logic Disconnect Timeout
TMDS181 TMDS181I start_stop_LASE75.gif Figure 18. START and STOP Condition Timing
TMDS181 TMDS181I tim_SCL_SDA_LASE75.gif Figure 19. SCL and SDA Timing
TMDS181 TMDS181I DDC_delay_source_LASE75.gif Figure 20. DDC Propagation Delay – Source to Sink
TMDS181 TMDS181I DDC_delay_sink_LASE75.gif Figure 21. DDC Propagation Delay – Sink to Source
TMDS181 TMDS181I ARC_output_LASE75.gif Figure 22. ARC Output
TMDS181 TMDS181I ARC_rise_fall_LASE75.gif Figure 23. Rise and Fall Time of ARC