The TMP100-Q1 and TMP101-Q1 devices are Two-Wire, SMBUs, and I²C interface-compatible. Figure 7-3 to Figure 7-6 describe the various operations on the TMP100-Q1 and TMP101-Q1. The following list provides bus definitions. Parameters for Figure 7-3 are defined in the Section 6.6 table.

Bus Idle: Both SDA and SCL lines remain HIGH.

Start Data Transfer: A change in the state of the SDA line, from HIGH to LOW, while the SCL line is HIGH, defines a START condition. Each data transfer is initiated with a START condition.

Stop Data Transfer: A change in the state of the SDA line from LOW to HIGH while the SCL line is HIGH defines a STOP condition. Each data transfer is terminated with a repeated START or STOP condition.

Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and is determined by the controller device. The receiver acknowledges the transfer of data.

Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the Acknowledge clock pulse. Setup and hold times must be taken into account. On a controller receive, the termination of the data transfer can be signaled by the controller generating a Not-Acknowledge on the last byte that is transmitted by the target.

Figure 7-3 I²C Timing Diagram

Figure 7-4 I²C Timing Diagram for Write Word Format

Figure 7-5 I²C Timing Diagram for Read Word Format

Figure 7-6 Timing Diagram for SMBus ALERT