JAJSFY5E August   2018  – December 2019 TMUX6111 , TMUX6112 , TMUX6113

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Thermal Information
    4. 8.4 Recommended Operating Conditions
    5. 8.5 Electrical Characteristics (Dual Supplies: ±15 V)
    6. 8.6 Switching Characteristics (Dual Supplies: ±15 V)
    7. 8.7 Electrical Characteristics (Single Supply: 12 V)
    8. 8.8 Switching Characteristics (Single Supply: 12 V)
    9. 8.9 Typical Characteristics
  9. 9 Parameter Measurement Information
    1. 9.1 Truth Tables
  10. 10Detailed Description
    1. 10.1 Overview
      1. 10.1.1  On-Resistance
      2. 10.1.2  Off-Leakage Current
      3. 10.1.3  On-Leakage Current
      4. 10.1.4  Break-Before-Make Delay
      5. 10.1.5  Turn-On and Turn-Off Time
      6. 10.1.6  Charge Injection
      7. 10.1.7  Off Isolation
      8. 10.1.8  Channel-to-Channel Crosstalk
      9. 10.1.9  Bandwidth
      10. 10.1.10 THD + Noise
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Ultra-low Leakage Current
      2. 10.3.2 Ultra-low Charge Injection
      3. 10.3.3 Bidirectional and Rail-to-Rail Operation
    4. 10.4 Device Functional Modes
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
    3. 11.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14デバイスおよびドキュメントのサポート
    1. 14.1 ドキュメントのサポート
      1. 14.1.1 関連資料
    2. 14.2 関連リンク
    3. 14.3 ドキュメントの更新通知を受け取る方法
    4. 14.4 サポート・リソース
    5. 14.5 商標
    6. 14.6 静電気放電に関する注意事項
    7. 14.7 Glossary
  15. 15メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.3.2 Ultra-low Charge Injection

The TMUX6111, TMUX6112, and TMUX6113 are implemented with simple transmission gate topology, as shown in Figure 28. Any mismatch in the stray capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is opened or closed. The devices utilize special charge-injection cancellation circuitry that reduces the source (Sx)-to-drain (Dx) charge injection to as low as 0.6 pC at VS = 0 V, as shown in Figure 29.

TMUX6111 TMUX6112 TMUX6113 Transmission_Gate.gifFigure 28. Transmission Gate Topology
TMUX6111 TMUX6112 TMUX6113 D007_SCDS383.gifFigure 29. Source-to-Drain Charge Injection vs Source or Drain Voltage