TPA3223 is designed as a feature-enhanced cost efficient high power Class-D audio amplifier. The device has built-in advanced protection circuitry to provide for maximum product robustness as well as a flexible feature set including selectable gain settings, switching frequency, clock synchronization of multiple devices, mute function, temperature and clipping status signals. TPA3223 has a bandwidth up to 100 kHz and low output noise designed for high resolution audio applications and accepts both differential and single ended analog audio inputs at levels from 1 V_RMS to 2 V_RMS. With the closed loop operation TPA3223 is designed for high audio performance with a system power supply between 10 V and 42 V.

An external 5 V supply is used for the AVDD and VDD supply pins. Although supplied from the same 5 V source, separating AVDD and VDD on the printed-circuit board (PCB) by RC filters (see Section 10.2 for details) is recommended. These RC filters provide the recommended high-frequency isolation. Special attention needs to be paid to placing all decoupling capacitors as close to their associated pins as possible. In general, the physical loop with the power supply pins, decoupling capacitors and GND return path to the device pins must be kept as short as possible and with as little area as possible to minimize induction (see Section 10.4.2 for additional information).

The floating supplies for the output stage high side gate drives are supplied by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge.

For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin (BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive power-supply pin (GVDD) and the bootstrap pins. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides an acceptable voltage supply for the high-side gate driver. TI recommends to use 33 nF ceramic capacitors, size 0603 or 0805, for the bootstrap supply. These 33 nF capacitors maintain sufficient energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining part of the PWM cycle.

Special attention needs to be paid to the power stage power supply; this includes component selection, PCB placement, and routing.

For good electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X node is decoupled with 1 μF ceramic capacitors placed as close as possible to the PVDD supply pins. TI recommends to follow the PCB layout of the TPA3223 reference design. For additional information on recommended power supply and required components, see Section 10.2.

The external power supply for the AVDD and VDD supplies must be from a low-noise, low-output-impedance voltage regulator. Likewise, the 42V power stage supply is assumed to have low output impedance throughout the entire audio band, and low noise. The power supply sequence is not critical as facilitated by the internal power-on-reset circuit, but TI recommends to release RESET after the power supply is settled for minimum turn on audible artifacts. Moreover, the TPA3223 is fully protected against erroneous power-stage turn on due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are noncritical within the specified range (see the Section 7.3 table of this data sheet).