SLVSAX6H October   2011  – December 2015 TPS2002C , TPS2003C , TPS2052C , TPS2060C , TPS2062C , TPS2062C-2 , TPS2064C , TPS2064C-2 , TPS2066C , TPS2066C-2

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: TJ = TA = 25°C
    6. 7.6 Electrical Characteristics: -40°C ≤ (TJ = TA) ≤ 125°C
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Undervoltage Lockout (UVLO)
      2. 9.3.2 Enable (ENx or ENx)
      3. 9.3.3 Deglitched Fault Reporting
      4. 9.3.4 Overcurrent Protection
      5. 9.3.5 Overtemperature Protection
      6. 9.3.6 Softstart, Reverse Blocking and Discharge Output
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Input and Output Capacitance
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Self-Powered and Bus-Powered Hubs
    2. 11.2 Low-Power Bus-Powered and High-Power Bus-Powered Functions
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Power Dissipation and Junction Temperature
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ

12 Layout

12.1 Layout Guidelines

  • Place the 100-nF bypass capacitor near the IN and GND pins, and make the connections using a low-inductance trace.
  • When large transient currents are expected on the output, TI recommends placing a high-value electrolytic capacitor and a 100-nF bypass capacitor on the output pin.
  • The PowerPAD should be directly connected to PCB ground plane using wide and short copper trace.

12.2 Layout Example

TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C layout_slvsa6.gif Figure 34. Layout Recommendation

12.3 Power Dissipation and Junction Temperature

It is good design practice to estimate power dissipation and maximum expected junction temperature of the TPS20xxC and TPS20xxC-2 dual. The system designer can control choices of package, proximity to other power dissipating devices, and printed circuit board (PCB) design based on these calculations. These have a direct influence on maximum junction temperature. Other factors such as airflow and maximum ambient temperature are often determined by system considerations.

Addition of extra PCB copper area around these devices is recommended to reduce the thermal impedance and maintain the junction temperature as low as practical.

The following procedure requires iteration because power loss is due to the two internal MOSFETs 2 × I2 × rDS(on), and rDS(on) is a function of the junction temperature. As an initial estimate, use the rDS(on) at 125°C from the typical characteristics, and the preferred package thermal resistance for the preferred board construction from the thermal parameters section.

Equation 1. TJ = TA + [2 × IOUT2 × rDS(on) × θJA]

where

  • IOUT = rated OUT pin current (A)
  • rDS(on) = Power switch on-resistance at an assumed TJ (Ω)
  • TA = Maximum ambient temperature (°C)
  • TJ = Maximum junction temperature (°C)
  • θJA = Thermal resistance (°C/W)

If the calculated TJ is substantially different from the original assumption, look up a new value of rDS(on) and recalculate.

If the resulting TJ is not less than 125°C, try a PCB construction and/or package with lower θJA.