JAJSJF1B March   2014  – September 2020 TPS2556-Q1 , TPS2557-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Terminal Configuration and Functions
    1.     Terminal Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
      1.      16
  8. 8 Parameter Measurement Information
    1.     18
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Overcurrent Conditions
      2. 9.3.2 FAULT Response
      3. 9.3.3 Thermal Sense
    4. 9.4 Device Functional Modes
      1. 9.4.1 Undervoltage Lockout (UVLO)
      2. 9.4.2 Enable ( EN OR EN)
      3. 9.4.3 Auto-Retry Functionality
      4. 9.4.4 Two-Level Current-Limit Circuit
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application, Design for Current Limit
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Determine Design Parameters
        2. 10.2.2.2 Programming the Current-Limit Threshold
        3. 10.2.2.3 Selecting Current-Limit Resistor 1
        4. 10.2.2.4 Selecting Current-Limit Resistor 2
        5. 10.2.2.5 Accounting for Resistor Tolerance
        6. 10.2.2.6 Power Dissipation and Junction Temperature
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1.     44
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.2 FAULT Response

Assertion (active-low) of the FAULT open-drain output occurs during an overcurrent or overtemperature condition. The TPS2556-Q1 and TPS2557-Q1 devices assert the FAULT signal until removal of the fault condition and the resumption of normal device operation. Design of the TPS2556-Q1 and TPS2557-Q1 devices eliminates false FAULT reporting by using an internal delay (9-ms typical) deglitch circuit for overcurrent conditions without the need for external circuitry. This avoids accidental FAULT assertion due to normal operation, such as starting into a heavy capacitive load. The deglitch circuitry delays entering and leaving current-limit-induced fault conditions. Deglitching of the FAULT signal does not occur when an overtemperature condition disables the MOSFET, but does occur after the device has cooled and begins to turn on. This unidirectional deglitch prevents FAULT oscillation during an overtemperature event.