JAJSCH0D August   2016  – January 2018 TPS25741 , TPS25741A

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      DFPホスト・ポートへの実装の簡略図
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 VBUS Capacitance
      2. 8.1.2 USB Data Communications
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  USB Type-C CC Logic (CC1, CC2)
      2. 8.3.2  9.3.2 VCONN Supply (VCONN, CC1, CC2)
      3. 8.3.3  USB Power Delivery BMC Transmission (CC1, CC2, VTX)
      4. 8.3.4  USB Power Delivery BMC Reception (CC1, CC2)
      5. 8.3.5  Discharging (DSCG, VPWR)
        1. 8.3.5.1 Discharging after a Fault (VPWR)
      6. 8.3.6  Configuring Voltage Capabilities (HIPWR, EN9V, EN12V)
      7. 8.3.7  Configuring Power Capabilities (PSEL, PCTRL, HIPWR)
      8. 8.3.8  Gate Drivers
        1. 8.3.8.1 GDNG, GDNS
        2. 8.3.8.2 G5V
        3. 8.3.8.3 GDPG
      9. 8.3.9  Fault Monitoring and Protection
        1. 8.3.9.1 Over/Under Voltage (VBUS)
        2. 8.3.9.2 Over-Current Protection (ISNS, VBUS)
        3. 8.3.9.3 System Fault Input (GD, VPWR)
      10. 8.3.10 Voltage Control (CTL1, CTL2)
      11. 8.3.11 Sink Attachment Indicator (UFP, DVDD)
      12. 8.3.12 Accessory Attachment Indicator (AUDIO, DEBUG)
      13. 8.3.13 Plug Polarity Indication (POL)
      14. 8.3.14 Power Supplies (VAUX, VDD, VPWR, DVDD)
      15. 8.3.15 Grounds (AGND, GND)
      16. 8.3.16 Output Power Supply (DVDD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode
      2. 8.4.2 Checking VBUS at Start Up
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 System-Level ESD Protection
      2. 9.1.2 Use of GD Internal Clamp
      3. 9.1.3 Resistor Divider on GD for Programmable Start Up
      4. 9.1.4 Selection of the CTL1 and CTL2 Resistors (RFBL1 and RFBL2)
      5. 9.1.5 Voltage Transition Requirements
      6. 9.1.6 VBUS Slew Control using GDNG CSLEW
      7. 9.1.7 Tuning OCP Using RF and CF
    2. 9.2 Typical Applications
      1. 9.2.1 A/C Multiplexing Power Source
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Power Pin Bypass Capacitors
          2. 9.2.1.2.2 Non-Configurable Components
          3. 9.2.1.2.3 Configurable Components
        3. 9.2.1.3 Application Curves
      2. 9.2.2 D/C Power Source
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Power Pin Bypass Capacitors
          2. 9.2.2.2.2 Non-Configurable Components
          3. 9.2.2.2.3 Configurable Components
        3. 9.2.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 A/C Power Source (Wall Adapter)
      2. 9.3.2 Dual-Port Power Managed A/C Power Source (Wall Adapter)
  10. 10Power Supply Recommendations
    1. 10.1 VDD
    2. 10.2 VCONN
    3. 10.3 VPWR
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Port Current Kelvin Sensing
      2. 11.1.2 Power Pin Bypass Capacitors
      3. 11.1.3 Supporting Components
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
    2. 12.2 関連リンク
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.7 Configuring Power Capabilities (PSEL, PCTRL, HIPWR)

The power advertised to non-Power Delivery Type-C Sinks is always 15 W. However, the TPS25741 or TPS25741A only advertises Type-C default current until it debounces the Sink attachment for tCcDeb and the VBUS voltage has been given tVP to stabilize.

The device does not communicate with the cable to determine its capabilities. Therefore, unless the device is in a system with a USB Type-C plug and a cable built to support 5 A, the HIPWR pin should be used to limit the advertised current to 3 A.

PCTRL is an input pin used to control how much of the maximum allowed power the port will advertise. This pin may be changed dynamically in the system and the device automatically updates any existing USB Power Delivery contract. If the PCTRL pin is pulled below VPCTRL_TH, then the source capabilities offers half of the maximum power specified by the PSEL pin.

The devices read the PSEL and HIPWR pins after a reset and latches the result, but the PCTRL pin is read dynamically by the device and if its state changes new capabilities are calculated and then transmitted.

While USB Power Delivery allows a maximum power of 100 W, the TPS25741 only advertises up to 93 W, which allows margin to ensure the output power remains below 100 W.

The PSEL pin offers four possible maximum power settings, but the devices can actually advertise more power settings depending upon the state of the HIPWR and PCTRL pins. Table 3 summarizes the four maximum power settings that are available via PSEL, again note this is not necessarily the maximum power that is advertised.

Table 3. PSEL Configurations

MAXIMUM POWER
(PSEL) [W] 		PSEL
PSEL = 36 Direct to GND
PSEL = 45 DVDD via RSEL
PSEL = 65 GND via RSEL
PSEL = 93 Direct to DVDD

The following list provides a quick reference which applies to both TPS25741 and TPS25741A to see how the HIPWR, PSEL, and PCTRL pins affect what current is advertised with each voltage in the source capabilities message:

  • If the PCTRL pin is low, then Pmax = PSEL/2
  • If the PCTRL pin is high, then Pmax = PSEL.
  • If the HIPWR pin is pulled high, then Imax = 3 A.
  • If the HIPWR pin is pulled low, then Imax = 5 A.
  • For a voltage Vx, the advertised current is Ix
    • Ix = min( Pmax/Vx, Imax)

Table 4 and Table 5 provide a comprehensive list of the currents and voltages that are advertised for each voltage.

Table 4. Maximum Current Advertised in the Power Data Object for a Given Voltage (TPS25741)

PSEL VOLTAGE [V] HIPWR MAXIMUM CURRENT
PCTRL = LOW [A]		 MAXIMUM CURRENT
PCTRL = HIGH [A]
Direct to GND 5 Max = 3 A
DVDD through RSEL or Direct to DVDD 		3 3
DVDD via RSEL 3 3
GND via RSEL 3 3
Direct to DVDD 3 3
Direct to GND 12 1.5 3
DVDD via RSEL 1.87 3
GND via RSEL 2.7 3
Direct to DVDD 3 3
Direct to GND 20 Max = 3 A
Direct to DVDD		 0.9 1.8
DVDD via RSEL 1.12 2.24
GND via RSEL 1.62 3
Direct to DVDD 2.32 3
Direct to GND 5 Max = 5 A
GND through RSEL or Direct to GND		 3.6 5
DVDD via RSEL 4.5 5
GND via RSEL 5 5
Direct to DVDD 5 5
Direct to GND 12 1.5 3
DVDD via RSEL 1.87 3.74
GND via RSEL 2.7 5
Direct to DVDD 4.16 5
Direct to GND 20 Max = 5 A
Direct to GND		 0.9 1.8
DVDD via RSEL 1.12 2.24
GND via RSEL 1.62 3.24
Direct to DVDD 2.32 4.64

Table 5. Maximum Current Advertised in the Power Data Object for a Given Voltage (TPS25741A)

PSEL VOLTAGE [V] HIPWR MAXIMUM CURRENT
PCTRL = LOW [A]		 MAXIMUM CURRENT
PCTRL = HIGH [A]
Direct to GND 5 Max = 3 A
DVDD through RSEL or Direct to DVDD 		3 3
DVDD via RSEL 3 3
GND via RSEL 3 3
Direct to DVDD 3 3
Direct to GND 9 2 3
DVDD via RSEL 2.5 3
GND via RSEL 3 3
Direct to DVDD 3 3
Direct to GND 15 Max = 3 A
Direct to DVDD		 1.2 2.4
DVDD via RSEL 1.5 3
GND via RSEL 2.17 3
Direct to DVDD 3 3
Direct to GND 5 Max = 5 A
GND through RSEL or Direct to GND		 3.6 5
DVDD via RSEL 4.5 5
GND via RSEL 5 5
Direct to DVDD 5 5
Direct to GND 9 2 4
DVDD via RSEL 2.5 5
GND via RSEL 3.61 5
Direct to DVDD 5 5
Direct to GND 15 Max = 5 A
Direct to GND		 1.2 2.4
DVDD via RSEL 1.5 3
GND via RSEL 2.17 4.34
Direct to DVDD 3.1 5