8.3.4 Reset Output

In a typical TPS3860x0 application, RESETn or RESETn outputs are connected to the reset input of a processor (DSP, CPU, FPGA, ASIC, and so forth), or connected to the enable input of a voltage regulator (DC-DC, LDO, and so forth).

The TPS386000 provides open-drain reset outputs. Pullup resistors must be used to hold these lines high when RESETn is not asserted, or when RESETn is asserted. By connecting pullup resistors to the proper voltage rails (up to 6.5 V), RESETn or RESETn output nodes can be connected to the other devices at the correct interface voltage levels. The pullup resistor should be no smaller than 10 kΩ to ensure the safe operation of the output transistors. By using wired-OR logic, any combination of RESETn can be merged into one logic signal.

The TPS386040 provides pushpull reset outputs. The logic high level of the outputs is determined by the V_DD voltage. With this configuration, pullup resistors are not required and some board area can be saved. However, all the interface logic levels should be examined. All RESETn or RESETn connections must be compatible with the V_DD logic level.

The RESETn or RESETn outputs are defined for V_DD voltage higher than 0.9 V. To ensure that the target processor(s) are properly reset, the V_DD supply input should be fed by the available power rail as early as possible in application circuits. Table 1, Table 2, Table 3, and Table 4 are truth tables that describe how the outputs are asserted or released. Figure 1, Figure 2, Figure 3, and Figure 4 show the SVS-n timing diagrams. When the conditions are met, the device changes the state of SVS-n from asserted to released after a user-configurable delay time. However, the transitions from released-state to asserted-state are performed almost immediately with minimal propagation delay. Figure 3 describes the relationship between threshold voltages (V_ITN and V_HYSN) and SENSEm voltage; and all SVS-1, SVS-2, SVS-3, and SVS-4 have the same behavior of Figure 3.