JAJSGC0F September   2009  – October 2018 TPS386000 , TPS386040

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      TPS386000代表的アプリケーション回路： FPGA電源の監視
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Voltage Monitoring
      2. 8.3.2 Manual Reset
      3. 8.3.3 Watchdog Timer
      4. 8.3.4 Reset Output
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Undervoltage Detection
      2. 9.1.2 Undervoltage and Overvoltage Detection
      3. 9.1.3 Sensing a Negative Voltage
      4. 9.1.4 Reset Delay Time
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
        1. 12.1.1.1 評価モジュール
        2. 12.1.1.2 SPICEモデル
      2. 12.1.2 デバイスの項目表記
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 関連リンク
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4 Device Functional Modes

The following tables show the state of the output and the status of the part under various conditions.

Table 1. SVS-1 Truth Table

CONDITION OUTPUT STATUS
MR = Low SENSE1 < VITN RESET1 = Low Reset asserted
MR = Low SENSE1 > VITN RESET1 = Low Reset asserted
MR = High SENSE1 < VITN RESET1 = Low Reset asserted
MR = High SENSE1 > VITN RESET1 = High Reset released after delay

Table 2. SVS-2 Truth Table

CONDITION OUTPUT STATUS
SENSE2 < VITN RESET2 = Low Reset asserted
SENSE2 > VITN RESET2 = High Reset released after delay

Table 3. SVS-3 Truth Table

CONDITION OUTPUT STATUS
SENSE3 < VITN RESET3 = Low Reset asserted
SENSE3 > VITN RESET3 = High Reset released after delay

Table 4. SVS-4 Truth Table

CONDITION OUTPUT STATUS
SENSE4L < VITN SENSE4H > VITP RESET4 = Low Reset asserted
SENSE4L < VITN SENSE4H < VITP RESET4 = Low Reset asserted
SENSE4L > VITN SENSE4H > VITP RESET4 = Low Reset asserted
SENSE4L > VITN SENSE4H < VITP RESET4 = High Reset released after delay

Table 5. Watchdog Timer (WDT) Truth Table

CONDITION OUTPUT STATUS
WDO WDO RESET1 WDI PULSE INPUT
Low High Asserted Toggling WDO = low Remains in WDT time-out
Low High Asserted 610 ms after last WDI↑ or WDI↓ WDO = low Remains in WDT time-out
Low High Released Toggling WDO = low Remains in WDT time-out
Low High Released 610 ms after last WDI↑ or WDI↓ WDO = low Remains in WDT time-out
High Low Asserted Toggling WDO = high Normal operation
High Low Asserted 610 ms after last WDI↑ or WDI↓ WDO = high Normal operation
High Low Released Toggling WDO = high Normal operation
High Low Released 610 ms after last WDI↑ or WDI↓ WDO = low Enters WDT timeout