JAJSGC0F September 2009 – October 2018 TPS386000 , TPS386040
PRODUCTION DATA.
Each of the SVS-n channels can be configured independently in one of three modes. Table 6 describes the delay time settings.
| CTn CONNECTION | DELAY TIME |
|---|---|
| Pullup to VDD | 300 ms (typical) |
| Open | 20 ms (typical) |
| Capacitor to GND | Programmable |
To select the 300-ms fixed delay time, the CTn pin should be pulled up to VDD using a resistor from 40 kΩ to 200 kΩ. There is a pulldown transistor from CTn to GND that turns on every time the device powers on to determine and confirm CTn pin status; therefore, a direct connection of CTn to VDD causes a large current flow. To select the 20-ms fixed delay time, the CTn pin should be left open. To program a user-defined adjustable delay time, an external capacitor must be connected between CTn and GND. The adjustable delay time can be calculated by the following equation:
Using this equation, a delay time can be set to between 1.4 ms to 10 s. The external capacitor should be greater than 220 pF (nominal) so that the TPS3860x0 can distinguish it from an open CT pin. The reset delay time is determined by the time it takes an on-chip, precision 300-nA current source to charge the external capacitor to 1.24 V. When the RESETn or RESETn outputs are asserted, the corresponding capacitors are discharged. When the condition to release RESETn or RESETn occurs, the internal current sources are enabled and begin to charge the external capacitors. When the CTn voltage on a capacitor reaches 1.24 V, the corresponding RESETn or RESETn pins are released. A low leakage type capacitor (such as ceramic) should be used, and that stray capacitance around this pin may cause errors in the reset delay time.