11.1 Layout Guidelines
Follow these guidelines to lay out the printed-circuit board (PCB) that is used for the TPS3860x family of devices.
- Keep the traces to the timer capacitors as short as possible to optimize accuracy.
- Avoid long traces from the SENSE pin to the resistor divider. Instead, run the long traces from the RSnH to VMON(n).
- Place the VDD decoupling capacitor (CVDD) close to the device.
- Avoid using long traces for the VDD supply node. The VDD capacitor (CVDD), along with parasitic inductance from the supply to the capacitor, can form an LC tank and create ringing with peak voltages above the maximum VDD voltage.