JAJSOH5D November   2022  – November 2023 TPS389C03-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  I2C
      2. 7.3.2  Maskable Interrupt (AMSK)
      3. 7.3.3  VDD
      4. 7.3.4  MON
      5. 7.3.5  NRST
      6. 7.3.6  NIRQ
      7. 7.3.7  ADC
      8. 7.3.8  Packet Error Checking (PEC)
      9. 7.3.9  Q&A Watchdog
        1. 7.3.9.1 Question and Token Generation
        2. 7.3.9.2 Q&A Watchdog Open and Close Window Delay
        3. 7.3.9.3 Q&A Watchdog Status Register
        4. 7.3.9.4 Q&A Watchdog Timing
        5. 7.3.9.5 Q&A Watchdog State Machine and Test Program
      10. 7.3.10 Error Signal Monitoring (ESM)
        1. 7.3.10.1 ESM Timing
    4. 7.4 Device Functional Modes
      1. 7.4.1 Built-In Self Test and Configuration Load
        1. 7.4.1.1 Notes on BIST Execution
      2. 7.4.2 TPS389C03-Q1 Power ON
  9. 8 Register Maps
    1. 8.1 Registers Overview
      1. 8.1.1 BANK0 Registers
      2. 8.1.2 BANK1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Automotive Multichannel Sequencer and Monitor
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supply Guidelines
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Documentation Support
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.10 Error Signal Monitoring (ESM)

The Error Signal Monitoring (ESM) pin is used to monitor the error output of the SOC or microcontroller. The internal types of errors that need to happen to assert the ESM pin low can be configured in the microcontroller. Once the ESM pin is asserted low, the actions or results of the microcontroller cannot be relied on. The ESM pin has a programmable threshold delay (Bank 1_0x09E_Threshold) to prevent unintended false trips. The ESM pin also has a configurable debounce (Bank 1_0x09F_ESM_DEB). When the ESM pin of TPS389C03-Q1 is asserted low an ESM_ERROR will be flagged by a bit located in the INT_VENDOR register. The ESM pin is pulled low by default through an internal 100k pull-down resistance, thus an ESM_ERROR will be flagged by default if no external source is applied to the ESM pin. Note the pull down resistor is only active when VDD has been applied, otherwise the pin is left floating.

Table 7-5 ESM Threshold Delay Time
REG VALUE TIME NOTES

0-31

1-32 ms

1 ms steps

32-63

34-96 ms

2 ms steps

64-255

100-864 ms

4 ms steps

The configurations listed in Table 7-6 to Table 7-12 demonstrate how TPS389C03-Q1 responds when mapped to different fault outputs such as NRST, NIRQ and WDO. Faults mapped to NIRQ are always latched. Faults mapped to WDO can be latched or have an associated WDO delay based on the OTP setting. If the ESM function is being used as a reset method, then it is recommended to map ESM to WDO to avoid NRST toggling. If WDE is pulled low in operation, it is recommended to have ESM fault mapped only to NIRQ.

When ESM is mapped to WDO, an ESM fault, with the resulting WDO assertion, will not be flagged in the WDT_ERROR bit. However, it is recommended to write 1 to the WDT_ERROR bit and the ESM_ERROR bit found in the INT_VENDOR (Section 8.1.1.9) register to clear all of the latched outputs. The WDO output can also be deasserted by toggling the WDE pin.

Table 7-6 ESM Mapped to WDO, NIRQ, and NRST
WDE WDO NIRQ NRST
ESM fault High After ESM delay, WDO asserted and ESM fault set. I2C write to clear and deassert. After ESM delay, NIRQ asserted and ESM fault set. I2C write to clear and deassert. After ESM delay, NRST asserted and deasserted after reset delay. ESM pin state not checked until WDO is deasserted.
Low ESM fault not asserted WDO. After ESM delay, NIRQ asserted and ESM fault set. I2C write to clear and deassert. After ESM delay, NRST asserted and deasserted after reset delay. ESM pin state checked after ESM delay. If ESM stays low, NRST will toggle.
Table 7-7 ESM Mapped to NIRQ and NRST
WDE WDO NIRQ NRST
ESM fault High Not asserted. After ESM delay, NIRQ asserted and ESM fault set. I2C write to clear and deassert. After ESM delay, NRST asserted and deasserted after reset delay. ESM pin state checked after ESM delay. If ESM stays low, NRST will toggle.
Low Not asserted. After ESM delay, NIRQ asserted and ESM fault set. I2C write to clear and deassert. After ESM delay, NRST asserted and deasserted after reset delay. ESM pin state checked after ESM delay. If ESM stays low, NRST will toggle.
Table 7-8 ESM Mapped to WDO and NIRQ
WDE WDO NIRQ NRST
ESM fault High After ESM delay, WDO asserted and ESM fault set. I2C write to clear and deassert. After ESM delay, NIRQ asserted and ESM fault set. I2C write to clear and deassert. Not asserted.
Low Not asserted. After ESM delay,NIRQ asserted and ESM fault set. I2C write to clear and deassert. Not asserted.
Table 7-9 ESM Mapped to WDO and NRST
WDE WDO NIRQ NRST
ESM fault High After ESM delay, WDO asserted and ESM fault set. I2C write to clear and deassert. Not asserted. After ESM delay, NRST asserted and deasserted after reset delay. ESM pin state not checked until WDO is deasserted.
Low Not asserted. Not asserted. After ESM delay, NRST asserted and deasserted after reset delay. ESM pin state checked after ESM delay. If ESM stays low NRST will toggle.
Table 7-10 ESM Mapped to NRST
WDE WDO NIRQ NRST
ESM fault High Not asserted. Not asserted. After ESM delay, NRST asserted and deasserted after reset delay. ESM pin state checked after ESM delay. If ESM stays low NRST will toggle.
Low Not asserted. Not asserted. After ESM delay, NRST asserted and deasserted after reset delay. ESM pin state checked after ESM delay. If ESM stays low NRST will toggle.
Table 7-11 ESM Mapped to NIRQ
WDE WDO NIRQ NRST
ESM fault High Not asserted. After ESM delay, NIRQ asserted and ESM fault set. I2C write to clear and deassert. Not asserted.
Low Not asserted. After ESM delay, NIRQ asserted and ESM fault set. I2C write to clear and deassert. Not asserted.
Table 7-12 ESM Mapped to WDO
WDE WDO NIRQ NRST
ESM fault High After ESM delay, WDO asserted and ESM fault set. I2C write to clear and deassert. Not asserted. Not asserted.
Low ESM fault not asserted WDO. Not asserted. Not asserted.