7.3.5 Power-Good

The TPS53513 device has power-good output that indicates high when switcher output is within the target. The power-good function is activated after the soft-start operation is complete. If the output voltage becomes within ±8% of the target value, internal comparators detect the power-good state and the power-good signal becomes high after a 1-ms internal delay. If the output voltage goes outside of ±16% of the target value, the power-good signal becomes low after a 2-μs internal delay. The power-good output is an open-drain output and must be pulled up externally.

In applications or end systems where PGOOD signal is needed by the load to sequence additional voltage supplies, take care to ensure both threshold and noise level/duration are within the design specification. This is especially true when the PGOOD signal is pulled up to the VREG supply. Because VREG is also being used to supply the internal FET gate drivers, during the active switching of the FETs, switching spikes associated with charging and discharging of the input parasitic capacitance of the FETs can be coupled on the VREG supply.

There are 3 intrinsic factors to consider:

1. Level of the spike. The typical spike level could be a few hundred millivolts below VREG. For worst case design, consider using –500 mV.
2. Duration of the spike. The worst case spike duration could reach 150 ns.
3. DC level of the VREG supply. The DC variation of VREG supply can be found in Electrical Characteristics.

Last, when laying out the TPS53513, follow the Layout Guidelines closely to minimize the noise impact to the VREG supply. In situations where layout cannot be optimized further, secure real-time measurement to ensure PGOOD design has sufficient margin.