JAJS461A October   2009  – November 2016 TPS54290 , TPS54291 , TPS54292

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Voltage Reference
      2. 8.3.2  Oscillator
      3. 8.3.3  Input UVLO and Start-Up
      4. 8.3.4  Enable and Timed Turnon of the Outputs
      5. 8.3.5  Soft Start
      6. 8.3.6  Output Voltage Regulation
      7. 8.3.7  Inductor Selection
      8. 8.3.8  Maximum Output Capacitance
      9. 8.3.9  Feedback Loop Compensation
      10. 8.3.10 Bootstrap for N-Channel MOSFET
      11. 8.3.11 Output Overload Protection
      12. 8.3.12 Operating Near Maximum Duty Cycle
      13. 8.3.13 Dual-Supply Operation
      14. 8.3.14 Bypassing and Filtering
    4. 8.4 Device Functional Modes
      1. 8.4.1 PWM Operation
      2. 8.4.2 Standby Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 TPS54291 Design Example
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Duty Cycle Estimation
          2. 9.2.1.2.2  Inductor Selection
          3. 9.2.1.2.3  Output Capacitor Selection
          4. 9.2.1.2.4  Input Capacitor Selection
          5. 9.2.1.2.5  Feedback
          6. 9.2.1.2.6  Compensation Components
          7. 9.2.1.2.7  Compensation Gain Setting Resistor
          8. 9.2.1.2.8  Compensation Integrator Capacitor
          9. 9.2.1.2.9  Bootstrap Capacitor
          10. 9.2.1.2.10 Power Dissipation
        3. 9.2.1.3 Application Curves
      2. 9.2.2 TPS54290 Cascaded Design Example
        1. 9.2.2.1 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PowerPAD™ Package
    2. 11.2 Layout Examples
    3. 11.3 Overtemperature Protection and Junction Temperature Rise
    4. 11.4 Power Derating
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 関連リンク
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

PWP Package
16-Pin HTSSOP
Top View

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
1 PVDD1 I Power input to the Output1 high-side MOSFET only. This pin must be locally bypassed to PGND1 with a low-ESR ceramic capacitor of 10 µF or greater. PVDD1 and PVDD2 could be tied externally together.
2 BOOT1 I Input supply to the high-side gate driver for Output1. Connect a 22-nF to 68-nF capacitor from this pin to SW1. This capacitor is charged from the BP pin voltage through an internal switch. The switch is turned ON during the off-time of the converter. To slow down the turn ON of the internal FET, a small resistor (2 Ω to 5 Ω) may be placed in series with the bootstrap capacitor.
3 SW1 O Source (switching) output for Output1 PWM
4 PGND1 — Power ground for Outputx. It is separated from GND to prevent the switching noise coupled to the internal logic circuits.
5 EN1 I Active-low enable input for Output1. If the voltage on this pin is greater than 1.5 V, Output1 is disabled (high-side switch is OFF). A voltage of less than 0.9 V enables Output1 and allow soft start of Output1 to begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin to GND to bypass the enable function.
6 EN2 I Active-low enable input for Output2. If the voltage on this pin is greater than 1.5 V, Output2 is disabled (high-side switch is OFF). A voltage of less than 0.9 V enables Output2 and allow soft start of Output2 to begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin to GND to bypass the enable function.
7 FB1 I Voltage feedback pin for Outputx. The internal transconductance error amplifier adjusts the PWM for Outputx to regulate the voltage at this pin to the internal 0.8-V reference. A series resistor divider from Outputx to ground, with the center connection tied to this pin, determines the value of the regulated output voltage.
8 COMP1 O Output of the transconductance (gM) amplifier. A R-C compensation network is connected from COMPx to GND.
9 COMP2 O Output of the transconductance (gM) amplifier. A R-C compensation network is connected from COMPx to GND.
10 FB2 I Voltage feedback pin for Outputx. The internal transconductance error amplifier adjusts the PWM for Outputx to regulate the voltage at this pin to the internal 0.8-V reference. A series resistor divider from Outputx to ground, with the center connection tied to this pin, determines the value of the regulated output voltage.
11 GND — Analog ground pin for the device.
12 BP — Regulated voltage to charge the bootstrap capacitors. Bypass this pin to GND with a low-ESR, 4.7-µF ceramic capacitor (10-µF capacitor preferred).
13 PGND2 — Power ground for Outputx. It is separated from GND to prevent the switching noise coupled to the internal logic circuits.
14 SW2 O Source (switching) output for Output2 PWM.
15 BOOT2 I Input supply to the high-side gate driver for Output2. Connect a 22-nF to 68-nF capacitor from this pin to SW2. This capacitor is charged from the BP pin voltage through an internal switch. The switch is turned ON during the off-time of the converter. To slow down the turn ON of the internal FET, a small resistor (2 Ω to 5 Ω) may be placed in series with the bootstrap capacitor.
16 PVDD2 I The PVDD2 pin provides power to the device control circuitry, provides the pullup for the EN1 and EN2 pins and provides power to the Output2 high-side MOSFET. This pin must be locally bypassed to PGND2 with a low-ESR ceramic capacitor of 10 µF or greater. The UVLO function monitors PVDD2 and enables the device when PVDD2 is greater than 4.2 V.
— Thermal Pad — This pad must be tied externally to a ground plane.