TPS5438x Dual 3-A Non-Synchronous Converters With Integrated High-Side MOSFET

1 Features

4.5-V to 28-V Input Range
Output Voltage Range 0.8 V to 90% of Input Voltage
Output Current Up to 3 A
Two Fixed Switching Frequency Versions:
- TPS54383: 300 kHz
- TPS54386: 600 kHz
Three Selectable Levels of Overcurrent Protection (Output 2)
0.8-V 1.5% Voltage Reference
2.1-ms Internal Soft-Start
Dual PWM Outputs 180° Out-of-Phase
Ratiometric or Sequential Startup Modes Selectable by a Single Pin
85-mΩ Internal High-Side MOSFETs
Current Mode Control
Internal Compensation (See Page 16)
Pulse-by-Pulse Overcurrent Protection
Thermal Shutdown Protection at +148°C
14-Pin PowerPAD™ HTSSOP package

2 Applications

Set Top Box
Digital TV
Power for DSP
Consumer Electronics

3 Description

The TPS54383 and TPS54386 are dual output, non-synchronous buck converters capable of supporting 3-A output applications that operate from a 4.5-V to 28-V input supply voltage, and require output voltages between 0.8 V and 90% of the input voltage.

With an internally-determined operating frequency, soft-start time, and control loop compensation, these converters provide many features with a minimum of external components. Channel 1 overcurrent protection is set at 4.5 A, while Channel 2 overcurrent protection level is selected by connecting a pin to ground, to BP, or left floating. The setting levels are used to allow for scaling of external components for applications that do not need the full load capability of both outputs.

The outputs may be enabled independently, or may be configured to allow either ratio-metric or sequential startup sequencing. Additionally, the two outputs may be powered from different sources.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
TPS54383	HTSSOP (14)	4.40 mm × 5.00 mm
TPS54386	HTSSOP (14)	4.40 mm × 5.00 mm

For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Schematic

4 Revision History

Changes from B Revision (October 2007) to C Revision

Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section.Go

5 Pin Configuration and Functions

PWP Package

14-Pin HTSSOP

Bottom View

Pin Functions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
BOOT1	2	I	Input supply to the high side gate driver for Output 1. Connect a 22-nF to 82-nF capacitor from this pin to SW1. This capacitor is charged from the BP pin voltage through an internal switch. The switch is turned ON during the OFF time of the converter. To slow down the turn ON of the internal FET, a small resistor (1 Ω to 3 Ω) may be placed in series with the bootstrap capacitor.
BOOT2	13	I	Input supply to the high side gate driver for Output 2. Connect a 22-nF to 82-nF capacitor from this pin to SW2. This capacitor is charged from the BP pin voltage through an internal switch. The switch is turned ON during the OFF time of the converter. To slow down the turn ON of the internal FET, a small resistor (1 Ω to 3 Ω) may be placed in series with the bootstrap capacitor.
BP	11	-	Regulated voltage to charge the bootstrap capacitors. Bypass this pin to GND with a low ESR (4.7-μF to 10-μF X7R or X5R) ceramic capacitor.
EN1	5	I	Active low enable input for Output 1. If the voltage on this pin is greater than 1.55 V, Output 1 is disabled (high-side switch is OFF). A voltage of less than 0.9 V enables Output 1 and allows soft-start of Output 1 to begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin to GND for "always ON" operation.
EN2	6	I	Active low enable input for Output 2. If the voltage on this pin is greater than 1.55 V, Output 2 is disabled (high-side switch is OFF). A voltage of less than 0.9 V enables Output 2 and allows soft-start of Output 2 to begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin to GND for "always ON" operation.
FB1	7	I	Voltage feedback pin for Output 1. The internal transconductance error amplifier adjusts the PWM for Output 1 to regulate the voltage at this pin to the internal 0.8-V reference. A series resistor divider from Output 1 to ground, with the center connection tied to this pin, determines the value of the regulated output voltage. Compensation for the feedback loop is provided internally to the device. See Feedback Loop and Inductor-Capacitor ( L-C) Filter Selection section for further information.
FB2	8	I	Voltage feedback pin for Output 2. The internal transconductance error amplifier adjusts the PWM for Output 2 to regulate the voltage at this pin to the internal 0.8-V reference. A series resistor divider from Output 2 to ground, with the center connection tied to this pin, determines the value of the regulated Output voltage. Compensation for the feedback loop is provided internally to the device. See Feedback Loop and Inductor-Capacitor ( L-C) Filter Selection section for further information.
GND	4	-	Ground pin for the device. Connect directly to Thermal Pad.
ILIM2	9	I	Current limit adjust pin for Output 2 only. This function is intended to allow a user with asymmetrical load currents (Output 1 load current much greater than Output 2 load current) to optimize component scaling of the lower current output while maintaining proper component derating in a overcurrent fault condition. The discrete levels are available as shown in Table 2. Note: An internal 2-resistor divider (150-kΩ each) connects BP to ILIM2 and to GND.
PVDD1	1	I	Power input to the Output 1 high side MOSFET only. This pin should be locally bypassed to GND with a low ESR ceramic capacitor of 10-μF or greater.
PVDD2	14	I	The PVDD2 pin provides power to the device control circuitry, provides the pull-up for the EN1 and EN2 pins and provides power to the Output 2 high-side MOSFET. This pin should be locally bypassed to GND with a low ESR ceramic capacitor of 10-μF or greater. The UVLO function monitors PVDD2 and enables the device when PVDD2 is greater than 4.1 V.
SEQ	10	I	This pin configures the output startup mode. If the SEQ pin is connected to BP, then when Output 2 is enabled, Output 1 is allowed to start after Output 2 has reached regulation; that is, sequential startup where Output 1 is slave to Output 2. If EN2 is allowed to go high after the outputs have been operating, then both outputs are disabled immediately, and the output voltages decay according to the load that is present. For this sequence configuration, tie EN1 to ground. If the SEQ pin is connected to GND, then when Output 1 is enabled, Output 2 is allowed to start after Output 1 has reached regulation; that is, sequential startup where Output 2 is slave to Output 1. If EN1 is allowed to go high after the outputs have been operating, then both outputs are disabled immediately, and the output voltages decay according to the load that is present. For this sequence configuration, tie EN2 to ground. If left floating, Output 1 and Output 2 start ratio-metrically when both outputs are enabled at the same time. They will soft-start at a rate determined by their final output voltage and enter regulation at the same time. If the EN1 and EN2 pins are allowed to operate independently, then the two outputs also operate independently NOTE: An internal two resistor (150-kΩ each) divider connects BP to SEQ and to GND. See the Sequence States table.
SW1	3	O	Source (switching) output for Output 1 PWM. A snubber is recommended to reduce ringing on this node. See SW Node Ringing for further information.
SW2	12	O	Source (switching) output for Output 2 PWM. A snubber is recommended to reduce ringing on this node. See SW Node Ringing for further information.
Thermal Pad	—	—	This pad must be tied externally to a ground plane and the GND pin.

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

		MIN	MAX	UNIT
Input voltage range	PVDD1, PVDD2, EN1, EN2		30	V
	BOOT1, BOOT2		V_SW+ 7
	SW1, SW2	–2	30
	SW1, SW2 transient (< 50ns)	–3	31
	BP		6.5
	SEQ, ILIM2	–0.3	6.5
	FB1, FB2	–0.3	3
	SW1, SW2 output current		7	A
	BP load current		35	mA
T_J	Operating temperature	–40	+150	°C
	Soldering temperature		+260	°C
T_stg	Storage temperature	–55	165	°C

(1) Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

			MIN	MAX	UNIT
V_PVDD2	Input voltage		4.5	28	V
T_J	Operating junction temperature		–40	+125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS54383 TPS54386	UNIT
		HTSSOP
		14 PINS
R_θJA	Junction-to-ambient thermal resistance	48.6	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	29.4
R_θJB	Junction-to-board thermal resistance	25.1
ψ_JT	Junction-to-top characterization parameter	0.9
ψ_JB	Junction-to-board characterization parameter	24.9
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	2.4

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

–40°C ≤ T_J ≤ +125°C, V_PVDD1 = V_PVDD2 = 12 V, unless otherwise noted.

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
INPUT SUPPLY (PVDD)
V_PVDD1	Input voltage range			4.5		28	V
V_PVDD2	Input voltage range			4.5		28	V
IDD_SDN	Shutdown		V_EN1 = V_EN2 = V_PVDD2		70	150	μA
IDD_Q	Quiescent, non-switching		V_FB = 0.9 V, Outputs off		1.8	3.0	mA
IDD_SW	Quiescent, while-switching		SW node unloaded; Measured as BP sink current		5		mA
V_UVLO	Minimum turn-on voltage		PVDD2 only	3.8	4.1	4.4	V
V_UVLO(hys)	Hysteresis				400		mV
t_START⁽¹⁾⁽²⁾	Time from startup to softstart begin		C_BP = 10 μF, EN1 and EN2 go low simultaneously		2		ms
ENABLE (EN)
V_EN1	Enable threshold			0.9	1.2	1.5	V
V_EN2	Enable threshold			0.9	1.2	1.5	V
	Hysteresis				50		mV
I_EN1	Enable pull-up current		V_EN1 = V_EN2 = 0 V		6	12	μA
I_EN2	Enable pull-up current		V_EN1 = V_EN2 = 0 V		6	12	μA
t_EN⁽¹⁾	Time from enable to soft-start begin		Other EN pin = GND		10		μs
BP REGULATOR (BP)
BP	Regulator voltage		8 V < P_VDD2 < 28 V	5	5.25	5.6	V
BP_LDO	Dropout voltage		P_VDD2 = 4.5 V; switching, no external load on BP		400		mV
I_BP⁽¹⁾	Regulator external load					2	mA
I_BPS	Regulator short circuit		4.5 V < P_VDD2 < 28 V	10	20	30	mA
OSCILLATOR
f_SW	Switching frequency	TPS54383		255	310	375	kHz
f_SW	Switching frequency	TPS54386		510	630	750	kHz
t_DEAD⁽¹⁾	Clock dead time				140		ns
ERROR AMPLIFIER (EA) and VOLTAGE REFERENCE (REF)
V_FB1	Feedback input voltage		0°C < T_J < +85°C	788	800	812	mV
V_FB2	Feedback input voltage		–40°C < T_J < +125°C	786		812	mV
I_FB1	Feedback input bias current				3	50	nA
I_FB2	Feedback input bias current				3	50	nA
g_M1⁽¹⁾	Transconductance				30		μS
g_M2⁽¹⁾	Transconductance				30		μS
SOFT-START (SS)
T_SS1	Soft-start time			1.5	2.1	2.7	ms
T_SS2	Soft-start time			1.5	2.1	2.7	ms
OVERCURRENT PROTECTION
I_CL1	Current limit channel 1			3.6	4.5	5.6	A
I_CL2	Current limit channel 2		V_ILIM2= V_BP	3.6	4.5	5.6
			V_ILIM2= (floating)	2.4	3.0	3.6
			V_ILIM2= GND	1.15	1.50	1.75
V_UV1	Low-level output threshold to declare a fault		Measured at feedback pin.		670		mV
V_UV2	Low-level output threshold to declare a fault		Measured at feedback pin.		670		mV
T_HICCUP⁽¹⁾	Hiccup timeout				10		ms
t_ON1(oc)⁽¹⁾	Minimum overcurrent pulse width				90	150	ns
t_ON2(oc)⁽¹⁾	Minimum overcurrent pulse width				90	150	ns
BOOTSTRAP
R_BOOT1	Bootstrap switch resistance		From BP to BOOT1 or BP to BOOT2, I_EXT = 50 mA		18		Ω
R_BOOT2	Bootstrap switch resistance		From BP to BOOT1 or BP to BOOT2, I_EXT = 50 mA		18		Ω
OUTPUT STAGE (Channel 1 and Channel 2)
R_DS(on)⁽¹⁾	MOSFET on resistance plus bond wire resistance		T_J = +25°C, V_PVDD2 = 8 V		85		mΩ
R_DS(on)⁽¹⁾	MOSFET on resistance plus bond wire resistance		–40°C < T_J < +125°C, V_PVDD2 = 8 V		85	165	mΩ
t_ON(min)⁽¹⁾	Minimum controllable pulse width		I_SWx peak current > 1 A⁽³⁾		100	200	ns
D_MIN	Minimum Duty Cycle		V_FB = 0.9 V			0	%
D_MAX	Maximum Duty Cycle	TPS54383	f_SW = 300 kHz	90	95		%
D_MAX	Maximum Duty Cycle	TPS54386	f_SW = 600 kHz	85	90		%
I_SW	Switching node leakage current (sourcing)		Outputs OFF		2	12	μA
THERMAL SHUTDOWN
T_SD⁽¹⁾	Shutdown temperature				148		°C
T_SD(hys)⁽¹⁾	Hysteresis				20		°C

(1) Ensured by design. Not production tested.

(2) When both outputs are started simultaneously, a 20-mA current source charges the BP capacitor. Faster times are possible with a lower BP capacitor value. More information can be found in the Input UVLO and Startup section.

(3) See Figure 14 for I_SWx peak current <1 A.