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The TPS54383 and TPS54386 are dual output, non-synchronous buck converters capable of supporting 3-A output applications that operate from a 4.5-V to 28-V input supply voltage, and require output voltages between 0.8 V and 90% of the input voltage.
With an internally-determined operating frequency, soft-start time, and control loop compensation, these converters provide many features with a minimum of external components. Channel 1 overcurrent protection is set at 4.5 A, while Channel 2 overcurrent protection level is selected by connecting a pin to ground, to BP, or left floating. The setting levels are used to allow for scaling of external components for applications that do not need the full load capability of both outputs.
The outputs may be enabled independently, or may be configured to allow either ratio-metric or sequential startup sequencing. Additionally, the two outputs may be powered from different sources.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS54383 | HTSSOP (14) | 4.40 mm × 5.00 mm |
TPS54386 |
Changes from B Revision (October 2007) to C Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
BOOT1 | 2 | I | Input supply to the high side gate driver for Output 1. Connect a 22-nF to 82-nF capacitor from this pin to SW1. This capacitor is charged from the BP pin voltage through an internal switch. The switch is turned ON during the OFF time of the converter. To slow down the turn ON of the internal FET, a small resistor (1 Ω to 3 Ω) may be placed in series with the bootstrap capacitor. |
BOOT2 | 13 | I | Input supply to the high side gate driver for Output 2. Connect a 22-nF to 82-nF capacitor from this pin to SW2. This capacitor is charged from the BP pin voltage through an internal switch. The switch is turned ON during the OFF time of the converter. To slow down the turn ON of the internal FET, a small resistor (1 Ω to 3 Ω) may be placed in series with the bootstrap capacitor. |
BP | 11 | - | Regulated voltage to charge the bootstrap capacitors. Bypass this pin to GND with a low ESR (4.7-μF to 10-μF X7R or X5R) ceramic capacitor. |
EN1 | 5 | I | Active low enable input for Output 1. If the voltage on this pin is greater than 1.55 V, Output 1 is disabled (high-side switch is OFF). A voltage of less than 0.9 V enables Output 1 and allows soft-start of Output 1 to begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin to GND for "always ON" operation. |
EN2 | 6 | I | Active low enable input for Output 2. If the voltage on this pin is greater than 1.55 V, Output 2 is disabled (high-side switch is OFF). A voltage of less than 0.9 V enables Output 2 and allows soft-start of Output 2 to begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin to GND for "always ON" operation. |
FB1 | 7 | I | Voltage feedback pin for Output 1. The internal transconductance error amplifier adjusts the PWM for Output 1 to regulate the voltage at this pin to the internal 0.8-V reference. A series resistor divider from Output 1 to ground, with the center connection tied to this pin, determines the value of the regulated output voltage. Compensation for the feedback loop is provided internally to the device. See Feedback Loop and Inductor-Capacitor ( L-C) Filter Selection section for further information. |
FB2 | 8 | I | Voltage feedback pin for Output 2. The internal transconductance error amplifier adjusts the PWM for Output 2 to regulate the voltage at this pin to the internal 0.8-V reference. A series resistor divider from Output 2 to ground, with the center connection tied to this pin, determines the value of the regulated Output voltage. Compensation for the feedback loop is provided internally to the device. See Feedback Loop and Inductor-Capacitor ( L-C) Filter Selection section for further information. |
GND | 4 | - | Ground pin for the device. Connect directly to Thermal Pad. |
ILIM2 | 9 | I | Current limit adjust pin for Output 2 only. This function is intended to allow a user with asymmetrical load currents (Output 1 load current much greater than Output 2 load current) to optimize component scaling of the lower current output while maintaining proper component derating in a overcurrent fault condition. The discrete levels are available as shown in Table 2. Note: An internal 2-resistor divider (150-kΩ each) connects BP to ILIM2 and to GND. |
PVDD1 | 1 | I | Power input to the Output 1 high side MOSFET only. This pin should be locally bypassed to GND with a low ESR ceramic capacitor of 10-μF or greater. |
PVDD2 | 14 | I | The PVDD2 pin provides power to the device control circuitry, provides the pull-up for the EN1 and EN2 pins and provides power to the Output 2 high-side MOSFET. This pin should be locally bypassed to GND with a low ESR ceramic capacitor of 10-μF or greater. The UVLO function monitors PVDD2 and enables the device when PVDD2 is greater than 4.1 V. |
SEQ | 10 | I | This pin configures the output startup mode. If the SEQ pin is connected to BP, then when Output 2 is enabled, Output 1 is allowed to start after Output 2 has reached regulation; that is, sequential startup where Output 1 is slave to Output 2. If EN2 is allowed to go high after the outputs have been operating, then both outputs are disabled immediately, and the output voltages decay according to the load that is present. For this sequence configuration, tie EN1 to ground. If the SEQ pin is connected to GND, then when Output 1 is enabled, Output 2 is allowed to start after Output 1 has reached regulation; that is, sequential startup where Output 2 is slave to Output 1. If EN1 is allowed to go high after the outputs have been operating, then both outputs are disabled immediately, and the output voltages decay according to the load that is present. For this sequence configuration, tie EN2 to ground. If left floating, Output 1 and Output 2 start ratio-metrically when both outputs are enabled at the same time. They will soft-start at a rate determined by their final output voltage and enter regulation at the same time. If the EN1 and EN2 pins are allowed to operate independently, then the two outputs also operate independently NOTE: An internal two resistor (150-kΩ each) divider connects BP to SEQ and to GND. See the Sequence States table. |
SW1 | 3 | O | Source (switching) output for Output 1 PWM. A snubber is recommended to reduce ringing on this node. See SW Node Ringing for further information. |
SW2 | 12 | O | Source (switching) output for Output 2 PWM. A snubber is recommended to reduce ringing on this node. See SW Node Ringing for further information. |
Thermal Pad | — | — | This pad must be tied externally to a ground plane and the GND pin. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Input voltage range | PVDD1, PVDD2, EN1, EN2 | 30 | V | |
BOOT1, BOOT2 | VSW+ 7 | |||
SW1, SW2 | –2 | 30 | ||
SW1, SW2 transient (< 50ns) | –3 | 31 | ||
BP | 6.5 | |||
SEQ, ILIM2 | –0.3 | 6.5 | ||
FB1, FB2 | –0.3 | 3 | ||
SW1, SW2 output current | 7 | A | ||
BP load current | 35 | mA | ||
TJ | Operating temperature | –40 | +150 | °C |
Soldering temperature | +260 | |||
Tstg | Storage temperature | –55 | 165 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1500 |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VPVDD2 | Input voltage | 4.5 | 28 | V | |
TJ | Operating junction temperature | –40 | +125 | °C |
THERMAL METRIC(1) | TPS54383 TPS54386 | UNIT | |
---|---|---|---|
HTSSOP | |||
14 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 48.6 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 29.4 | |
RθJB | Junction-to-board thermal resistance | 25.1 | |
ψJT | Junction-to-top characterization parameter | 0.9 | |
ψJB | Junction-to-board characterization parameter | 24.9 | |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 2.4 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
INPUT SUPPLY (PVDD) | |||||||
VPVDD1 | Input voltage range | 4.5 | 28 | V | |||
VPVDD2 | |||||||
IDDSDN | Shutdown | VEN1 = VEN2 = VPVDD2 | 70 | 150 | μA | ||
IDDQ | Quiescent, non-switching | VFB = 0.9 V, Outputs off | 1.8 | 3.0 | mA | ||
IDDSW | Quiescent, while-switching | SW node unloaded; Measured as BP sink current | 5 | ||||
VUVLO | Minimum turn-on voltage | PVDD2 only | 3.8 | 4.1 | 4.4 | V | |
VUVLO(hys) | Hysteresis | 400 | mV | ||||
tSTART(1)(2) | Time from startup to softstart begin | CBP = 10 μF, EN1 and EN2 go low simultaneously | 2 | ms | |||
ENABLE (EN) | |||||||
VEN1 | Enable threshold | 0.9 | 1.2 | 1.5 | V | ||
VEN2 | |||||||
Hysteresis | 50 | mV | |||||
IEN1 | Enable pull-up current | VEN1 = VEN2 = 0 V | 6 | 12 | μA | ||
IEN2 | |||||||
tEN(1) | Time from enable to soft-start begin | Other EN pin = GND | 10 | μs | |||
BP REGULATOR (BP) | |||||||
BP | Regulator voltage | 8 V < PVDD2 < 28 V | 5 | 5.25 | 5.6 | V | |
BPLDO | Dropout voltage | PVDD2 = 4.5 V; switching, no external load on BP | 400 | mV | |||
IBP(1) | Regulator external load | 2 | mA | ||||
IBPS | Regulator short circuit | 4.5 V < PVDD2 < 28 V | 10 | 20 | 30 | ||
OSCILLATOR | |||||||
fSW | Switching frequency | TPS54383 | 255 | 310 | 375 | kHz | |
TPS54386 | 510 | 630 | 750 | ||||
tDEAD(1) | Clock dead time | 140 | ns | ||||
ERROR AMPLIFIER (EA) and VOLTAGE REFERENCE (REF) | |||||||
VFB1 | Feedback input voltage | 0°C < TJ < +85°C | 788 | 800 | 812 | mV | |
VFB2 | –40°C < TJ < +125°C | 786 | 812 | ||||
IFB1 | Feedback input bias current | 3 | 50 | nA | |||
IFB2 | |||||||
gM1(1) | Transconductance | 30 | μS | ||||
gM2(1) | |||||||
SOFT-START (SS) | |||||||
TSS1 | Soft-start time | 1.5 | 2.1 | 2.7 | ms | ||
TSS2 | |||||||
OVERCURRENT PROTECTION | |||||||
ICL1 | Current limit channel 1 | 3.6 | 4.5 | 5.6 | A | ||
ICL2 | Current limit channel 2 | VILIM2 = VBP | 3.6 | 4.5 | 5.6 | ||
VILIM2 = (floating) | 2.4 | 3.0 | 3.6 | ||||
VILIM2 = GND | 1.15 | 1.50 | 1.75 | ||||
VUV1 | Low-level output threshold to declare a fault | Measured at feedback pin. | 670 | mV | |||
VUV2 | |||||||
THICCUP(1) | Hiccup timeout | 10 | ms | ||||
tON1(oc)(1) | Minimum overcurrent pulse width | 90 | 150 | ns | |||
tON2(oc)(1) | |||||||
BOOTSTRAP | |||||||
RBOOT1 | Bootstrap switch resistance | From BP to BOOT1 or BP to BOOT2, IEXT = 50 mA |
18 | Ω | |||
RBOOT2 | |||||||
OUTPUT STAGE (Channel 1 and Channel 2) | |||||||
RDS(on)(1) | MOSFET on resistance plus bond wire resistance | TJ = +25°C, VPVDD2 = 8 V | 85 | mΩ | |||
–40°C < TJ < +125°C, VPVDD2 = 8 V | 85 | 165 | |||||
tON(min)(1) | Minimum controllable pulse width | ISWx peak current > 1 A(3) | 100 | 200 | ns | ||
DMIN | Minimum Duty Cycle | VFB = 0.9 V | 0 | % | |||
DMAX | Maximum Duty Cycle | TPS54383 | fSW = 300 kHz | 90 | 95 | % | |
TPS54386 | fSW = 600 kHz | 85 | 90 | % | |||
ISW | Switching node leakage current (sourcing) | Outputs OFF | 2 | 12 | μA | ||
THERMAL SHUTDOWN | |||||||
TSD(1) | Shutdown temperature | 148 | °C | ||||
TSD(hys)(1) | Hysteresis | 20 |