JAJSM00A May   2023  – February 2024 TPS543B25

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  VIN Pins and VIN UVLO
      2. 6.3.2  Internal Linear Regulator and Bypassing
      3. 6.3.3  Enable and Adjustable UVLO
        1. 6.3.3.1 Internal Sequence of Events During Start-Up
      4. 6.3.4  Switching Frequency Selection
      5. 6.3.5  Switching Frequency Synchronization to an External Clock
        1. 6.3.5.1 Internal PWM Oscillator Frequency
        2. 6.3.5.2 Loss of Synchronization
        3. 6.3.5.3 Interfacing the SYNC/FSEL Pin
      6. 6.3.6  Remote Sense Amplifier and Adjusting the Output Voltage
      7. 6.3.7  Loop Compensation Guidelines
        1. 6.3.7.1 Output Filter Inductor Tradeoffs
        2. 6.3.7.2 Ramp Capacitor Selection
        3. 6.3.7.3 Output Capacitor Selection
        4. 6.3.7.4 Design Method for Good Transient Response
      8. 6.3.8  Soft Start and Prebiased Output Start-Up
      9. 6.3.9  MSEL Pin
      10. 6.3.10 Power Good (PG)
      11. 6.3.11 Output Overload Protection
        1. 6.3.11.1 Positive Inductor Current Protection
        2. 6.3.11.2 Negative Inductor Current Protection
      12. 6.3.12 Output Overvoltage and Undervoltage Protection
      13. 6.3.13 Overtemperature Protection
      14. 6.3.14 Output Voltage Discharge
    4. 6.4 Device Functional Modes
      1. 6.4.1 Forced Continuous-Conduction Mode
      2. 6.4.2 Discontinuous Conduction Mode During Soft Start
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 1.0-V Output, 1-MHz Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 7.2.1.2.2  Switching Frequency
          3. 7.2.1.2.3  Output Inductor Selection
          4. 7.2.1.2.4  Output Capacitor
          5. 7.2.1.2.5  Input Capacitor
          6. 7.2.1.2.6  Adjustable Undervoltage Lockout
          7. 7.2.1.2.7  Output Voltage Resistors Selection
          8. 7.2.1.2.8  Bootstrap Capacitor Selection
          9. 7.2.1.2.9  VDRV and VCC Capacitor Selection
          10. 7.2.1.2.10 PGOOD Pullup Resistor
          11. 7.2.1.2.11 Current Limit Selection
          12. 7.2.1.2.12 Soft-Start Time Selection
          13. 7.2.1.2.13 Ramp Selection and Control Loop Stability
          14. 7.2.1.2.14 MODE Pin
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
      3. 7.4.3 Thermal Performance
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Custom Design With WEBENCH® Tools
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

GUID-20211110-SS0I-7QWH-3JLS-BBDKMXFQ1R06-low.svgFigure 4-1 17-Pin WQFN-FCRLF RYS Package (Bottom View)
GUID-20211116-SS0I-766Z-GTKL-TWXCXPNJZWPX-low.svgFigure 4-2 17-Pin WQFN-FCRLF RYS Package
(Top View)
Table 4-1 Pin Functions
Pin Type(1) Description
Name No.
AGND 1 — Ground return for internal analog circuits

VCC

 2 I Supply for analog control circuitry. Connect a 10-Ω resistor from VDRV to this pin and bypass with a 0.1-μF capacitor to AGND.
VDRV 3 O Internal 5-V regulator output and internal connection to drivers. Bypass these pins with a 2.2-μF capacitor to PGND. See Section 6.3.2.
VIN 4, 9 I Input power to the power stage. Low impedance bypassing of these pins to PGND is critical. A 1-μF capacitor from each VIN to PGND close to the IC is required.
PGND 5, 8, 16, 17 — Ground return for the power stage. This pin is internally connected to the source of the low-side MOSFET.
SW 6 O Switch node of the converter. Connect this pin to the output inductor.
BOOT 7 I Supply for the internal high-side MOSFET gate driver. Connect a capacitor from this pin to SW.
EN 10 I Enable pin. Float or tie high to enable, or enable and disable with an external signal, or adjust the input undervoltage lockout with a resistor divider. See Section 6.3.3.
PG 11 O Open-drain power-good indicator. See Section 6.3.10.
SYNC/FSEL 12 I Frequency select and external clock synchronization. A resistor to ground sets the switching frequency of the device. An external clock can also be applied to this pin to synchronize the switching frequency. See Section 6.3.5.3.
MSEL 13 I A resistor to ground selects the current limit, soft-start rate, and PWM ramp amplitude. See Section 6.3.9.
GOSNS 14 I Ground sense return and input to the differential remote sense amplifier
FB 15 I Feedback pin and input to the differential remote sense amplifier for output voltage regulation. Connect this pin to the midpoint of a resistor divider to set the output voltage. See Section 6.3.6.
(1) I = input, O = output