JAJSIO3A February 2020 – September 2020 TPS546B24A
PRODUCTION DATA
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | ||
| 1 | PGD/RST_B | I/O | Open-drain power good or Section 7.6.19 RESET#. As determined by user-programmable RESET# bit in Section 7.6.83. The default pin function is an open-drain power-good indicator. When configured as RESET#, an internal pullup can be enabled or disabled by the PULLUP# bit in Section 7.6.83. |
| 2 | PMB_DATA | I/O | PMBus DATA pin. See Current PMBus Specifications. |
| 3 | PMB_CLK | I | PMBus CLK pin. See Current PMBus Specifications. |
| 4 | BP1V5 | O | Output of the 1.5-V internal regulator. This regulator powers the digital circuitry and should be bypassed with a minimum of 1 µF to DRTN with an X5R or better ceramic capacitor rated for a minimum of 6 V. BP1V5 is not designed to power external circuit. |
| 5 | DRTN | — | Digital bypass return for bypass capacitor for BP1V5. Internally connected to AGND. Do not connect to PGND or AGND. |
| 6 | SMB_ALRT | O | SMBus alert pin. See SMBus specification. |
| 7 | BOOT | I | Bootstrap pin for the internal flying high side driver. Connect a typical 100-nF X5R or better ceramic capacitor rated for a minimum of 10 V from this pin to SW. To reduce the voltage spike at SW, an optional BOOT resistor of up to 8 Ω can be placed in series with the BOOT capacitor to slow down turn-on of the high-side FET. |
| 8 | SW | I/O | Switched power output of the device. Connect the output averaging filter and bootstrap to this group of pins. |
| 9 | |||
| 10 | |||
| 11 | |||
| 12 | |||
| 13 | PGND | — | Power stage ground return. These pins are internally connected to the thermal pad. |
| 14 | |||
| 15 | |||
| 16 | |||
| 17 | |||
| 18 | |||
| 19 | |||
| 20 | |||
| 21 | PVIN | I | Input power to the power stage. Low-impedance bypassing of these pins to PGND is critical. PVIN to PGND should be bypassed with X5R or better ceramic capacitors rated for at least 1.5x the maximum PVIN voltage. In addition, a minimum of one 0402 2.2-nF - 10-nF X7R or better ceramic capacitance rated for at least 1.5x the maximum PVIN voltage should placed as close to the PVIN and PGND pins or under the PVIN pins to reduce the high-frequency bypass impedance. |
| 22 | |||
| 23 | |||
| 24 | |||
| 25 | |||
| 26 | AVIN | I | Input power to the controller. Bypass with a minimum 1-µF X5R or better ceramic capacitor rated for at least 1.5x the maximum AVIN voltage to AGND. If AVIN is connected to the same input as PVIN or VDD5, a minimum 10-µs R-C filter between PVIN or VDD5 and AVIN is recommended to reduce switching noise on AVIN. |
| 27 | EN/UVLO | I | Enable switching as the PMBus CONTROL pin. EN/UVLO can also be connected to a resistor divider to program input voltage UVLO. |
| 28 | VDD5 | O | Output of the 5-V internal regulator. This regulator powers the driver stage of the controller and should be bypassed with a minimum of 4.7-µF X5R or better ceramic capacitor rated for a minimum of 10 V to PGND at the thermal pad. Low impedance bypassing of this pin to PGND is critical. |
| 29 | MSEL2 | I | Connect this pin to a 1% tolerance or better resistor divider between BP1V5 and AGND for different options of soft-start time, overcurrent fault limit, and multi-phase information. See Section 7.5.2.2 or Section 7.5.2.5 if GOSNS is tied to BP1V5. |
| 30 | VSEL | I | Connect this pin to a 1% tolerance or better resistor divider between BP1V5 and AGND for different options of internal voltage feedback divider and default output voltage. See Section 7.5.2.3. |
| 31 | ADRSEL | I | Connect this pin to a 1% tolerance or better resistor divider between BP1V5 and AGND for different options of PMBus addresses and frequency sync (including determination of SYNC pin as SYNC IN or SYNC OUT function). See Section 7.5.2.4. |
| 32 | MSEL1 | I | Connect this pin to a 1% tolerance or better resistor divider between BP1V5 and AGND for different options of switching frequency and internal compensation parameters. See Section 7.5.2.1. |
| 33 | VOSNS | I | The positive input of the remote sense amplifier. For a stand-alone device or the loop master device in a multi-phase configuration, connect VOSNS pin to the output voltage at the load. For the loop slave device in a multi-phase configuration, the remote sense amplifier is not required for output voltage sensing or regulation and this pin can be left floating. If used to monitor another voltage with the Phased READ_VOUT command, VOSNS should be maintained between 0 V and 0.75 V with a <1-kΩ resistor divider due to the internal resistance to GOSNS, which is connected to BP1V5. |
| 34 | GOSNS/SLAVE | I | The negative input of the remote sense amplifier for loop master device or should be pulled up high to indicate loop slave. For a standalone device or the loop master device in a multi-phase configuration, connect the GOSNS pin to the ground at the load. For the loop slave device in a multi-phase configuration, the GOSNS pin must be pulled up to BP1V5 to indicate the device a loop slave. |
| 35 | VSHARE | I/O | Voltage sharing signal for multi-phase operation. For standalone device, the VSHARE pin must be left floating. VSHARE can by bypassed to AGND with up to 50 pF of capacitance. |
| 36 | NC | - | Not internally connected. Connect to PGND at the thermal pad. |
| 37 | AGND | - | Analog ground return for controller. Connect the AGND pin directly to the thermal pad on the PCB board. |
| 38 | SYNC | I/O | For frequency synchronization, can be programmed as SYNC IN or SYNC OUT pin by ADRSEL pin or the Section 7.6.81 PMBus Command. The SYNC pin can be left floating when not used. |
| 39 | BCX_CLK | I/O | Clock for back-channel communications between stacked devices |
| 40 | BCX_DAT | I/O | Data for back-channel communications between stacked devices |
| — | Thermal pad | — | Package thermal pad, internally connected to PGND. The thermal pad must have adequate solder coverage for proper operation. |