JAJSN95A august   2022  – may 2023 TPS563252 , TPS563257

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PWM Operation and D-CAP3™ Control Mode
      2. 7.3.2 Eco-mode Control
      3. 7.3.3 Soft Start and Prebiased Soft Start
      4. 7.3.4 Overvoltage Protection
      5. 7.3.5 Large Duty Operation
      6. 7.3.6 Current Protection and Undervoltage Protection
      7. 7.3.7 Undervoltage Lockout (UVLO) Protection
      8. 7.3.8 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Eco-mode Operation
      2. 7.4.2 FCCM Mode Operation
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Output Voltage Resistors Selection
        3. 8.2.2.3 Output Filter Selection
        4. 8.2.2.4 Input Capacitor Selection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Custom Design With WEBENCH® Tools
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Electrical Characteristics

TJ = –40°C to 125°C, VIN = 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY VOLTAGE
VIN Input voltage range VIN 3 17 V
IVIN VIN supply current No load, VEN = 5 V, VFB = 0.65 V, non-switching, ECO version 100 µA
No load, VEN = 5 V, VFB = 0.65 V, non-switching, FCCM version 370 µA
IINSDN VIN shutdown current No load, VEN = 0 V 2 µA
UVLO
VIN_UVLO Input undervoltage lockout threshold Rising threshold 2.80 2.92 3.00 V
Falling threshold 2.60 2.72 2.80 V
Hysteresis 200 mV
FEEDBACK VOLTAGE
VREF FB voltage TJ = 25°C 594 600 606 mV
TJ = –40°C to 125°C 591 600 609 mV
INTEGRATED POWER MOSFETS
RDSON_HS High-side MOSFET on-resistance TJ = 25°C, VIN ≥ 5 V 55.0
TJ = 25°C, VIN = 3 V (1) 67.5
RDSON_LS Low-side MOSFET on-resistance TJ = 25°C, VIN ≥ 5 V 24.3
TJ = 25°C, VIN = 3 V 30.2
SWITCHING FREQUENCY
fsw Switching frequency TJ = 25°C, VOUT = 3.3 V 1.2 MHz
tON(MIN)(1) Minimum on time 60 ns
tOFF(MIN)(1) Minimum off time VFB = 0.5 V 110 ns
LOGIC THRESHOLD
VENH EN threshold high level Rising enable threshold 1.15 1.19 1.25 V
VENL EN threshold low level Falling disable threshold 0.90 1.00 1.10 V
VENHYS EN hystersis Hysteresis 190 mV
REN EN pulldown resistor 2
CURRENT LIMIT
IOCL_LS Overcurrent threshold Valley current set point 3.1 4.1 5.0 A
INOC Negtive overcurrent threshold 1.5 2.1 2.5 A
SOFT START
tSS Internal soft start time 1.6 ms
OUTPUT OVERVOLTAGE AND UNDERVOLTAGE PROTECTION
VOVP OVP trip threshold VFB rising 110% 115% 120%
tOVPDLY OVP prop deglitch 24 μs
VUVP UVP trip threshold VFB falling 55% 60% 65%
tUVPDLY UVP prop deglitch 220 μs
tUVPEN Hiccup enable delay time UVP detect 14 ms
POWER GOOD
VPGTH Power good threshold FB falling, PG from high to low 80% 85% 90%
FB rising, PG from low to high 85% 90% 95%
FB falling, PG from low to high 105% 110% 115%
FB rising, PG from high to low 110% 115% 120%
VPG(OL) PG pin output low-level voltage IOL = 4 mA 0.4 V
IPG(LKG) PG pin leakage current when open drain output is high VPG = 5.5 V 1 μA
tPG(R) PG delay going from low to high 1 ms
tPG(F) PG delay going from high to low 28 μs
THERMAL SHUTDOWN
TSDN(1) Thermal shutdown threshold Shutdown temperature 155 °C
TOTPHSY(1) Hysteresis 20
Specified by design