JAJSEQ9E November   2013  – December 2017 TPS56520 , TPS56720 , TPS56920 , TPS56C20

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション回路
  4. 4 改訂履歴
  5. 5 概要(続き)
  6. 6 List of Devices
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
    2.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Switching Characteristics
    8. 8.8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 PWM Operation
      2. 9.3.2 PWM Frequency and Adaptive On-Time Control
      3. 9.3.3 VIN and Power VIN Terminals (VIN and PVIN)
      4. 9.3.4 Auto-Skip Eco-mode™ Control
      5. 9.3.5 Soft Start and Pre-Biased Soft Start
      6. 9.3.6 Power Good
      7. 9.3.7 Overcurrent Protection
      8. 9.3.8 UVLO Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation at Light Loads
    5. 9.5 Programming
      1. 9.5.1 I2C Interface
      2. 9.5.2 I2C Protocol
      3. 9.5.3 I2C Chip Address Byte
    6. 9.6 Register Maps
      1. 9.6.1 I2C Register Address Byte
      2. 9.6.2 Output Voltage Registers
      3. 9.6.3 CheckSum Bit (VOUT Register Only)
      4. 9.6.4 Control Registers
      5. 9.6.5 Latchoff
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 TPS56520, TPS56720 and TPS56920, 5-A, 7-A, and 9-A Converter
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Output Voltage Resistors Selection
            1. 10.2.1.2.1.1 Output Filter Selection
          2. 10.2.1.2.2 Input Capacitor Selection
          3. 10.2.1.2.3 Bootstrap Capacitor Selection
          4. 10.2.1.2.4 VREG5 Capacitor Selection
      2. 10.2.2 TPS56520, TPS56720 and TPS56920 Application Performance Curves
      3. 10.2.3 TPS56C20 12-A Converter
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Design Procedure
        3. 10.2.3.3 TPS56C20 Application Performance Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 開発サポート
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 関連リンク
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PWP|20
サーマルパッド・メカニカル・データ
発注情報

8.5 Electrical Characteristics

TJ = –40°C to 125°C, VIN=4.5V to 17V, PVIN=4.5V to 17V (Unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE
VIN Operating input voltage VIN, PVIN 4.5 17 V
IIN VIN supply current 25°C, EN=5V, VFB=0.8V (non switching), VIN=12V 920 1150 µA
IVINSDN VIN shutdown current 25°C, EN=0V, VIN=12V 140 200 µA
FEEDBACK VOLTAGE
VVFB VFB voltage 25°C, external regulation mode, PVIN=12V, VOUT=1.1V, IOUT=50mA, pulse skipping 0.594 0.6 0.606 V
25°C, external regulation mode, VOUT=1.1V, continuous current mode 0.594 0.6 0.606 V
External regulation mode, VOUT=1.1V, continuous current mode 0.591 0.6 0.609 V
VOUT VOLTAGE (INTERNAL VID CONTROL)
VVOUT VOUT voltage 25°C, relative to target VOUT, PVIN=12V, VOUT=0.6V~1.87V, LOUT=1.5µH –1% 0% 1% Target VOUT
Relative to target VOUT, PVIN=12V, LOUT=1.5µH –1.5% 0% 1.5%
Relative to target VOUT, LOUT=1.5µH –2% 0% 2%
VREG5 OUTPUT
VVREG5 VREG5 Output Voltage 25°C , 6V< VIN <17V, IVREG5 = 5mA, VFB=1V 5.2 5.5 5.7 V
MOSFET
rDS(on)H High side switch resistance TPS56520 VBST-SW=5.5V 44 mΩ
rDS(on)L Low side switch resistance TPS56520 VIN=12V 32 mΩ
rDS(on)H High side switch resistance TPS56720 VBST-SW=5.5V 30 mΩ
rDS(on)L Low side switch resistance TPS56720 VIN=12V 24 mΩ
rDS(on)H High side switch resistance TPS56920 VBST-SW=5.5V 26 mΩ
rDS(on)L Low side switch resistance TPS56920 VIN=12V 19 mΩ
rDS(on)H High side switch resistance TPS56C20 VBST-SW=5.5V 13 mΩ
rDS(on)L Low side switch resistanceTPS56C20 VIN=12V 9 mΩ
POWER GOOD
VPGOODTH PGOOD threshold VOUT or VFB falling (fault) VO=1.1V 80%
VOUT or VFB rising (good) VO=1.1V 85%
VOUT or VFB rising (fault) VO=1.1V 115%
VOUT or VFB falling (good) VO=1.1V 110%
IPGOODDLY PGOOD sink current VPGOOD=0.5V 3.15 5.2 mA
LOGIC THRESHOLD
VENH EN H-level threshold voltage 1.85 V
VENL EN L-level threshold voltage 0.6 V
CURRENT LIMIT(1)
IOCL Current Limit TPS56520 LOUT= 1.5µH 5.6 9 A
Current Limit TPS56720 LOUT= 1.5µH 7.8 12 A
Current Limit TPS56920 LOUT= 1.5µH 10 15 A
Current Limit TPS56C20 LOUT= 1.5µH 13.2 20 A
IOCLR Reverse Current Limit TPS56520 LOUT= 1.5µH 1.25 5.3 A
Reverse Current Limit TPS56720 LOUT= 1.5µH 1.75 6.5 A
Reverse Current Limit TPS56920 LOUT= 1.5µH 2.25 6.2 A
Reverse Current Limit TPS56C20 LOUT= 1.5µH 3 8.2 A
OUTPUT UNDERVOLTAGE PROTECTION (UVP)
VOVP Output OVP trip threshold OVP detect (L>H) 125% VOUT
VUVP Output UVP trip threshold UVP detect (H>L) 60% VOUT
THERMAL SHUTDOWN
TSDN Thermal shutdown Threshold Shutdown temperature(1) 160 °C
Hysteresis(1) 23 °C
Pre-thermal warning threshold 130 °C
UVLO
UVLO UVLO Threshold Wake up to VREG5 voltage 3.45 3.9 4.2 V
Hysteresis VREG5 voltage 0.45 0.56 0.61 V
(1) Ensured by design. Not production tested.