JAJSEQ9E November   2013  – December 2017 TPS56520 , TPS56720 , TPS56920 , TPS56C20

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション回路
  4. 4 改訂履歴
  5. 5 概要(続き)
  6. 6 List of Devices
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
    2.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Switching Characteristics
    8. 8.8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 PWM Operation
      2. 9.3.2 PWM Frequency and Adaptive On-Time Control
      3. 9.3.3 VIN and Power VIN Terminals (VIN and PVIN)
      4. 9.3.4 Auto-Skip Eco-mode™ Control
      5. 9.3.5 Soft Start and Pre-Biased Soft Start
      6. 9.3.6 Power Good
      7. 9.3.7 Overcurrent Protection
      8. 9.3.8 UVLO Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation at Light Loads
    5. 9.5 Programming
      1. 9.5.1 I2C Interface
      2. 9.5.2 I2C Protocol
      3. 9.5.3 I2C Chip Address Byte
    6. 9.6 Register Maps
      1. 9.6.1 I2C Register Address Byte
      2. 9.6.2 Output Voltage Registers
      3. 9.6.3 CheckSum Bit (VOUT Register Only)
      4. 9.6.4 Control Registers
      5. 9.6.5 Latchoff
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 TPS56520, TPS56720 and TPS56920, 5-A, 7-A, and 9-A Converter
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Output Voltage Resistors Selection
            1. 10.2.1.2.1.1 Output Filter Selection
          2. 10.2.1.2.2 Input Capacitor Selection
          3. 10.2.1.2.3 Bootstrap Capacitor Selection
          4. 10.2.1.2.4 VREG5 Capacitor Selection
      2. 10.2.2 TPS56520, TPS56720 and TPS56920 Application Performance Curves
      3. 10.2.3 TPS56C20 12-A Converter
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Design Procedure
        3. 10.2.3.3 TPS56C20 Application Performance Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 開発サポート
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 関連リンク
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PWP|20
サーマルパッド・メカニカル・データ
発注情報

7 Pin Configuration and Functions

TPS56520/720/920
20-Pin PWP Package with PowerPAD
(TOP VIEW)
TPS56C20 TPS56920 TPS56720 TPS56520 PWP_pinout_520_720_920_SLVSCB6.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NUMBER
EN 1 I Enable. Pull High to enable converter.
SDA 2 I/O Data I/O terminal.
SCL 3 I/O Clock I/O terminal.
A1, A0 4,5 I Chip address.
VIN 6 I Supply Input for 5.5V linear regulator.
PVIN 7,8 I Power inputs and connects to high side MOSFET drains.
PGND 9,10 I/O Ground returns for low-side MOSFETs. Input of current comparator.
SW 11,12,13 I/O Switch node connections for both the high-side NFETs and low-side NFETs. Input of current comparator.
VBST 14 I Supply input for high-side NFET gate drive circuit. Connect 0.1µF ceramic capacitor between VBST and SW terminals. An internal diode is connected between VREG5 and VBST.
PGOOD 15 O Open drain power good output. Low means the output voltage of the corresponding output is out of regulation.
VREG5 16 O Output of 5.5V linear regulator. Bypass to GND with a high-quality ceramic capacitor of at least 2.0µF ceramic capacitor. Do not connect any other circuitry to the terminal. VREG5 is active when EN is H-level.
GND 17 I/O Signal GND. Connect sensitive SS and VFB returns to GND at a single point.
SS 18 O Soft-Start Programming terminal. Connect Capacitor from SS terminal to GND to program Soft-Start time.
VOUT 19 I Connection to output voltage
VFB 20 I D-CAP2 feedback input. Connect to output voltage with resistor divider.
Exposed Thermal Pad Back side I/O Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be connected to GND.
TPS56C20
24-Pin PWP Package with PowerPAD
(TOP VIEW)
TPS56C20 TPS56920 TPS56720 TPS56520 PWP_pinout_C20_SLVSCB6.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NUMBER
EN 1 I Enable. Pull High to enable according converter.
SDA 2 I/O Data I/O terminal.
SCL 3 I/O Clock I/O terminal.
A1, A0 4,5 I Chip address.
VIN 6 I Supply Input for 5.5V linear regulator.
PVIN 7,8 I Power inputs and connects to both high side NFET drains.
PGND 9,10,11,12 I/O Ground returns for low-side MOSFETs. Input of current comparator.
SW 13,14,15, 16, 17 I/O Switch node connections for both the high-side NFETs and low-side NFETs. Input of current comparator.
VBST 18 I Supply input for high-side NFET gate drive circuit. Connect 0.1µF ceramic capacitor between VBST and SW terminals. An internal diode is connected between VREG5 and VBST.
PGOOD 19 O Open drain power good output. Low means the output voltage of the corresponding output is out of regulation.
VREG5 20 O Output of 5.5V linear regulator. Bypass to GND with a high-quality ceramic capacitor of at least 3.0µF ceramic capacitor. Do not connect any other circuitry to the terminal. VREG5 is active when EN is H-level.
GND 21 I/O Signal GND. Connect sensitive SS and VFB returns to GND at a single point.
SS 22 O Soft-Start Programming terminal. Connect Capacitor from SS terminal to GND to program Soft-Start time.
VOUT 23 I Connection to output voltage
VFB 24 I D-CAP2 feedback inputs. Connect to output voltage with resistor divider.
Exposed Thermal Pad Back side I/O Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be connected to GND.