JAJSEQ9E November 2013 – December 2017 TPS56520 , TPS56720 , TPS56920 , TPS56C20
PRODUCTION DATA.
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The TPS56X20 implements a subset of the Phillips I2C specification Ver. 1.1. The TPS56X20 is a Slave-Only (it never becomes a Master, and so never pulls down the SCL terminal on the I2C bus). An I2C transaction consists of either writing a data byte to one of the TPS56X20’s internal registers which requires a 3-byte transaction or reading back one byte from a register which requires a 4-byte transaction. The protocols follow the System Management Bus (SMBUS) Specification Ver. 2.0 Write Byte and Read Byte protocols. This spec is available on the Internet for further reading, but the subset implemented in TPS56X20 is described below.
Long-form address modes, multi-byte data transfers and Packet Error Code (PEC) protocols are not supported in this implementation, though a Check Sum bit unique to the TPS56X20 is implemented and described below. The SMBUS Send Byte protocol (the 2-byte protocol used in TPS56921) is not implemented on TPS56X20.
The I2C interface terminals are composed of the SDA (Data) and SCL (Clock) terminals, and the A0 and A1 terminals to set up the chip’s address. SDA and SCL are designed to be used with pullup resistors to 3.3V. A0 and A1 are designed to be either grounded (logic LOW) or left open (logic HIGH) and should not tie to a high voltage.